Boots – shoes – and leggings
Patent
1986-12-17
1992-11-17
Shaw, Gareth D.
Boots, shoes, and leggings
364DIG1, 3642319, 364229, 3642285, 364239, 364284, 3642843, G06F 1300, G06F 1580
Patent
active
051650231
ABSTRACT:
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.
REFERENCES:
patent: 4598400 (1986-07-01), Hillis
Dally et al., "The Torus Routing Chip," Journal of Distributed Computing, vol. 1, No. 3, 1986.
Kermani et al., "Virtual Cut-Through: A New Computer Communication Switching Technique," Computer Networks, vol. 3, 1979, pp. 267-286.
Gottlieb et al., "The NYU Ultracomputer-Designing an MIMD Shared Memory Parallel Computer," IEEE Transactions on Computers, vol. C-32, No. 2, 1983, pp. 175-189.
Kulik Paul
Massachusetts Institute of Technology
Shaw Gareth D.
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