Patent
1995-01-17
1997-07-15
Harrell, Robert B.
G06F 9355
Patent
active
056491352
ABSTRACT:
A parallel processing system and method is disclosed, which provides an improved instruction distribution mechanism for a parallel processing array. The invention broadcasts a basic instruction to each of a plurality of processor elements. Each processor element decodes the same instruction by combining it with a unique offset value stored in each respective processor element, to produce a derived instruction that is unique to the processor element. A first type of basic instruction results in the processor element performing a logical or control operation. A second type of basic instruction results in the generation of a pointer address. The pointer address has a unique address value because it results from combining the basic instruction with the unique offset value stored at the processor element. The pointer address is used to access an alternative instruction from an alternative instruction storage, for execution in the processor element. The alternative instruction is a very long instruction word, whose length is, for example, an integral multiple of the length of the basic instruction and contains much more information than can be represented by the basic instruction. A very long instruction word such as this is useful for providing parallel control of a plurality of primitive execution units that reside within the processor element. In this manner, a high degree of flexibility and versatility is attained in the operation of processor elements of a parallel processing array.
REFERENCES:
patent: 4109311 (1978-08-01), Blum et al.
patent: 4394736 (1983-07-01), Bernstein et al.
patent: 4814978 (1989-03-01), Dennis
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5163139 (1992-11-01), Haigh et al.
patent: 5197135 (1993-03-01), Eickemeyer et al.
patent: 5274815 (1993-12-01), Trissel et al.
patent: 5299321 (1994-03-01), Iizuka
patent: 5303356 (1994-04-01), Vassiliadis et al.
patent: 5303358 (1994-04-01), Baum
Martin Gold, "Signal Path: TI's Competitive Edge", Electrical Engineering Times, Mar. 28, 1994, p. 68.
Glossner Clair John
Larsen Larry D.
Pechanek Gerald G.
Vassiliadis Stamatis
Harrell Robert B.
Hoel John E.
International Business Machines - Corporation
Phillips Steven B.
LandOfFree
Parallel processing system and method using surrogate instructio does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel processing system and method using surrogate instructio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processing system and method using surrogate instructio will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1499266