Boots – shoes – and leggings
Patent
1985-10-31
1989-07-11
Chan, Eddie P.
Boots, shoes, and leggings
364229, G06F 1516, G06F 1300
Patent
active
048477559
ABSTRACT:
A computer processing system containing a plurality of processor elements operates on a statically compiled program which, based upon detected natural concurrencies in the basic blocks of the programs, includes intelligence regarding logical processor allocation and an instruction firing time in the instruction stream. Each processor element, in one embodiment, is context free and is capable of executing instructions on a per instruction basis so that dependent instructions can execute on the same or different processor elements. A processor element is capable of executing an instruction from one context followed by an instruction from another context through use of shared storage resources.
REFERENCES:
patent: 3343135 (1967-09-01), Freiman et al.
patent: 3611306 (1971-10-01), Reigel
patent: 3771141 (1973-11-01), Culler
patent: 4104720 (1978-08-01), Gruner
patent: 4109311 (1978-08-01), Blum et al.
patent: 4153932 (1979-05-01), Dennis et al.
patent: 4181936 (1980-01-01), Kober
patent: 4228495 (1980-10-01), Bernhard
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4241398 (1980-12-01), Caril
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4430707 (1984-02-01), Kim
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4466061 (1984-08-01), DeSantis
patent: 4468736 (1984-08-01), DeSantis
patent: 4514807 (1985-04-01), Nogi
patent: 4574348 (1986-03-01), Scallon
Dennis, "Data Flow Supercomputers", Computer, Nov., 1980, pp. 48-56.
Hagiwara, H. et al., "A Dynamically Microprogrammable, Local Host Computer with Low-Level Parallelism", IEEE Transactions on Computers, C-29, No. 7, Jul., 1980, pp. 577-594.
Fisher et al., "Microcode Compaction: Looking Backward and Looking Forward", National Computer Conference, 1981, pp. 95-102.
Fisher et al., "Using an Oracle to Measure Potential Parallelism in Single Instruction Stream Programs", IEEE No. 0194-1895/0000/0171, 14th Annual Microprogramming Workshop, Sigmicro, Oct., 1981, pp. 171-182.
J. R. Vanaken et al., "The Expression Processor", IEEE Transactions on Computers, C-30, No. 8, Aug., 1981, pp. 525-536.
Bernhard, "Computing at the Speed Limit", IEEE Spectrum, Jul., 1982, pp. 26-31.
Davis, "Computer Architecture", IEEE Spectrum, Nov., 1983, pp. 94-99.
Hagiwara, H. et al., "A User-Microprogrammable Local Host Computer with Low-Level Parallelism", Article, Association for Computing Machinery, #0149-7111/83/0000/0151, 1983, pp. 151-157.
McDowell, Charles Edward, "SIMAC: A Multiple ALU Computer", Dissertation Thesis, University of California, San Diego, 1983, (111 pages).
McDowell, Charles E., "A Simple Architecture for Low Level Parallelism", Proceedings of 1983 International Conference on Parallel Processing, pp. 472-477.
Requa, et al., "The Piecewise Data Flow Architecture: Architectual Concepts", IEEE Transactions on Computers, vol. C-32, No. 5, May, 1983, pp. 425-438.
Fisher, A. T., "The VLIW Machine: A Multiprocessor for Compiling Scientific Code", Computer, 1984, pp. 45-52.
Fisher et al., "Measuring the Parallelism Available for Very Long Instruction, Word Architectures", IEEE Transactions on Computers, vol. C-33, No. 11, Nov., 1984, pp. 968-976.
Brooks Christopher B.
Gluck Frederick G.
Morrison Gordon E.
Chan Eddie P.
MCC Development, Ltd.
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