Parallel processing device to operate with parallel execute inst

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3642318, 364DIG1, G06F 938

Patent

active

052993213

ABSTRACT:
A parallel processing device consists of plural processing pipelines arranged in parallel, decoders which decode processing instructions and outputs them to respective processing pipelines, and a general register in which the processing instruction to be outputted to each of decoders is written in one of its registering sections, or a multiple-port register. The processing instructions are written in the general register or the multiple-port register, wherein the respective registering sections storing the processing instructions are simultaneously specified either by a parallel instruction device, a one-dimensional expanded instruction register, or a two-dimensional expanded instruction register so that their contents are simultaneously outputted to make each of the processing pipelines perform simultaneously. Thus, the simultaneous concentration of a large amount of information can be avoided during the parallel processing operation, eliminating the need for a bus with a large bit number.

REFERENCES:
patent: 4942525 (1990-07-01), Shintani et al.

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