Parallel processing decision-feedback equalizer (DFE) with...

Details Parallel processing decision-feedback equalizer (DFE) with... Parallel processing decision-feedback equalizer (DFE) with...

1999-06-04

2001-02-20

Vo, Don N. (Department: 2734)

Pulse or digital communications

Equalizers

Automatic

C708S323000

Reexamination Certificate

active

06192072

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to channel equalization techniques, and more particularly, to decision-feedback equalizers (DFEs) employing parallel (block) processing.
BACKGROUND OF THE INVENTION
Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. Thus, receivers must jointly equalize the channel, to compensate for such intersymbol interference (ISI) and other distortions, and decode the encoded signals at increasingly high clock rates. Decision-feedback equalization (DFE) is a widely-used technique for removing intersymbol interference where noise enhancement caused by a linear feed-forward equalizer (FFE) may introduce performance problems. For a detailed discussion of decision feedback equalizers (DFEs), see, for example, R. Gitlin et al., Digital Communication Principles, (Plenum Press 1992) and E. A. Lee and D. G. Messerschmitt, Digital Communications, (Kluwer Academic Press, 1988), each incorporated by reference herein. Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously decided symbols. Since DFE techniques are nonlinear, the DFE process does not enhance the channel noise.
In many high-speed applications, such as Fast Ethernet 100BASE-TX, mass storage, Gigabit Ethernet, or Synchronous Optical Networks (SONET), the symbol rates are high. For example, the Fast Ethernet 100BASE-TX standard uses a clock rate of 125 MHz. Thus, the equalization and decoding computations performed by the DFE must be performed at a clock period of 8 nanoseconds. Other advanced data networking applications, such as the SONET standard, may require even shorter clock periods. In many cases, such a short clock period makes the implementation of a DFE challenging or infeasible and forms the critical path in their implementation.
A number of methods have been proposed or suggested for speeding up the DFE processing. For example, K. Parhi, “Pipelining in Algorithm with Quantizer Loops”.
IEEE Transactions on Circuits and Systems
, Vol. 38, No. 7, 745-54 (July 1991), incorporated by reference herein, proposes a look-ahead architecture. Generally, a look-ahead DFE implementation transforms the original DFE feedback loop into a look-ahead structure (with duplicate DFEs for each possible value) and a simple loop with only a large selection multiplexor and one memory device. The look-ahead technique precomputes the symbol value for each possible variation, then utilizes the multiplexor to select the appropriate symbol when the actual value is determined. The complexity of the look-ahead implementation is M
L
, where M is the size of symbol alphabet, and L is the number of coefficient taps in the DFE. The speed of the look-ahead method is limited by a select-and-latch operation in the transformed simple loop.
Block (parallel) processing techniques have also been proposed for speeding up adaptive filters for high-speed communication applications. For a discussion of block processing techniques, see, for example, G. A. Clark et al., “Block Implementation of Adaptive Digital Filters”, Trans. on ASSP, Vol. ASSP-29, No. 3, (June 1981), incorporated by reference herein. Generally, block processing increases the throughput of the system by processing several inputs (made available through proper buffering) in one clock cycle using duplicated hardware. In return, the clock speed can be set at a lower and more feasible speed. For example, if ten inputs are processed in the same clock cycle, the processing clock speed can be lowered to ten percent (10%) of the clock speed of the received signal, while maintaining the same throughput.
While block processing techniques effectively reduce the required processing speed for general adaptive filter applications, block processing cannot easily be directly used with DFEs because of an output dependency in the feedback loop of DFEs. In the feedback loop of a DFE, each output depends on previous output values that may not be available from the previous cycle. As apparent from the above-described deficiencies with conventional DFEs, a need exists for a technique that reduces the output dependency and further speeds up DFE processing. U.S. patent application Ser. No. 09/206,527, filed Dec. 7, 1998, entitled “A Parallel Processing Decision-Feedback Equalizer (DFE),” assigned to the assignee of the present invention and incorporated by reference herein (hereinafter referred to as “the Azadet 7-4 System”), discloses a parallel implementation of a DFE that speeds up DFE processing. While the Azadet 7-4 System employs look-ahead techniques in each of a plurality of parallel blocks to achieve performance gains, the output dependencies in the disclosed parallel DFE nonetheless produce a delay on the order of N, where N is the number of blocks.
SUMMARY OF THE INVENTION
Generally, a method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The parallel DFE of the Azadet 7-4 System receives a plurality of symbol blocks in parallel using a plurality of corresponding input branches and utilizes look-ahead techniques within a given block to precompute all possible output values for the given block. The present invention extends the Azadet 7-4 System by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency.
The present invention reduces the delay in the critical path for parallel DFEs by employing block processing and look-ahead techniques in the selection (multiplexing) stage to select the actual output values from among the generated possible values. According to one aspect of the invention, the parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs.
According to another aspect of the invention, the disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. The present invention permits a pipeline implementation of the disclosed multiplexor array circuit, because there are no dependencies from one row of the multiplexor array to another row and the select signal, y
0
, is needed only at the bottom row of multiplexors. Pipeline latches can be added after any row of multiplexors in the multiplexor array circuit and each pipelined segment of the multiplexor array can be processed simultaneously. The number of pipeline segments that can be formed is between 2 and logN, where N is the number of parallel blocks.
The disclosed multiplexor tree circuitry for the parallel decision-feedback equalizer (DFE) groups multiplexor blocks into groups of two, referred to as block pairs, and provides at least one multiplexor for each block, i, to select an output value, y
i
, from among the possible precomputed values. In addition, block pairs are also progressively grouped into block groups, such that the first block group has one block pair, the second block group has two block pairs, and so on. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for the block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows according to N·logN, where N is the block number.
For example, the first block is not influenced by previous blocks and requires only

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