Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1998-12-07
2002-03-26
Pham, Chi (Department: 2631)
Pulse or digital communications
Equalizers
Automatic
C375S232000, C708S322000, C708S323000
Reexamination Certificate
active
06363112
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to digital signal processing and more specifically to a decision feedback equalizer employing a parallel processing arrangement.
BACKGROUND OF THE INVENTION
There is an ever increasing demand for digital signal processors that can operate at higher and higher clock rates. In many applications—such as mass storage devices or such as those governed by Fast Ethernet 100BASE-TX and proposed 1000BASE-T Gigabit Ethernet standards—require operation at extremely high symbol rates. For example, devices employing the 100BASE-TX standard use a 125 MHz clock, which requires powerful computation capacity.
One approach to alleviate the need for such powerful computation capacity is to employ parallel processing architecture. Conceptually, in parallel processing architecture, the computation task is divided into many portions or sub-tasks. A plurality of processors operate in parallel at lower clock rates to complete their allocated portion of the task. The results from each processor are then combined to complete the required computation.
One drawback to the parallel processing approach occurs in circumstances where a feedback loop is employed. The output being calculated by one processor depends on a previous value, which may not be available until a later time. As a result the system would fail to meet its time constraints.
An example of a system that employs a feedback loop is decision feedback equalizer. Typically, a decision feedback equalizer makes use of data decisions that have already been made, to provide improved performance. Decision feedback equalizer may be employed in communication and data transfer systems, wherein a plurality of data symbols are transmitted to a receiving device. The impulse response of the communication channel can cause intersymbol interference at the receiving device.
FIG. 1
is a typical impulse response of a communication channel after some linear preprocessing. Each component h(n) of the impulse response affects the received sample r(n) such that
r
(
n
)
=
h
(
0
)
t
(
n
)
+
∑
m
>
0
t
(
n
-
m
)
h
(
m
)
(
1
)
wherein t(n) is the current sample being transmitted. It is noted that the first term in equation (1) is the desired data symbol. The second term is known as post-cursor samples or previously detected data or previous decisions. These post-cursor samples are the cause of post-cursor intersymbol interference.
FIG. 2
illustrates a block diagram of a decision feedback equalizer
10
that is employed to substantially eliminate post-cursor intersymbol interference. A subtractor
12
is configured to receive data symbols r(n). The output port of subtractor
12
is coupled to the input port of slicer
14
. Slicer
14
is employed to assign a value corresponding to the received symbol. The output port of slicer
14
is coupled to a tapped delay line
16
, which is configured to generate a decision feedback signal defined by a sum of decision feedback components as explained in more detail below. The output port of tapped delay line
16
is coupled to a second input port of subtractor
12
.
During operation, the improved reception of the current data symbol r(n) is achieved by subtracting the effect of the prior decisions from the current sample. The input to slicer
14
is given by
s
(
n
)
=
r
(
n
)
-
∑
m
>
0
h
(
m
)
d
(
n
-
m
)
(
2
)
wherein d(n) is decision samples generated at the output port of slicer
14
. Assuming that the prior decision samples d(n) are computed correctly,
s(n)=h(0)t(n) (3).
Since it may be necessary to process signals at an extremely high clock rate, the computational steps employed in the decision feedback equalizer discussed above may not be completed within the appropriate time frames. This follows because, for example, tapped delay line
16
performs a convolution operation which involves addition and multiplication operations.
Thus, there is a need for a system and a method that can process the computational steps, similar to one discussed above, at extremely high clock rates.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a parallel processing decision feedback equalizer is configured to receive a plurality of symbol blocks in parallel via a plurality of corresponding input branches. The equalizer is configured to generate a plurality of decision symbol blocks, based on prior decisions generated in response to prior symbol blocks received by the filter. An input buffer stores the decision symbols that correspond to one or more prior symbol blocks. A storage buffer stores the, L, tap coefficients h(l) of the equalizer.
The first branch of the equalizer receives the first input signal of an incoming symbol block. The next branch of the equalizer receives the next input signal of an incoming signal block. Finally, the last branch of the equalizer receives the last input signal of an incoming signal block. Those branches of the equalizer that require the decisions from a previous branch, include a plurality of look-ahead-processors.
Each branch includes a tapped delay calculator that calculates a first portion of a decision feedback signal, which is the weighted sum of decision symbols based on prior symbol decisions stored in the input buffer and the tap coefficients stored in the storage buffer. The first portion of the decision feedback signal is then provided to the corresponding look-ahead processor in each branch. Each look-ahead-processor has a depth equal to the sequence order of the corresponding input signal within a symbol block. Each look-ahead processor calculates the remaining components of the decision feedback signal based on all possible combinations of decision samples that could be generated in prior branches. As a result each look-ahead processor makes available all possible components of the decision feedback signal based on all the possible results that could be provided from the prior branches.
The look-ahead processor in each branch is coupled to one or more selectors so as to select one of the calculated and available decision symbols based on the actual decision symbols calculated from previous branches. As a result, each branch rather than waiting to begin its calculations after it has received the results from the previous branch, performs its calculations before hand and waits for the results from the previous branches only for selecting one of the results that it has already calculated.
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Heung-No Lee and Greory J. Pottie, “Fast Adaptive Equalization/Diversity Combining for Time-Varying Dispersive Channels”, IEEE Transaction on Communications, vol. 46, No. 9, Sep. 1998, pp. 1146-1162.*
James E. C. Brown and Paul J. Hurst, “Continuous-Time Forward Equalization for the Decision-Feedback-Equalizer-Based Read Channel”, IEEE Transaction on Magnetics, vol. 34, No. 4, Jul. 1998, pp. 2372-2381.*
Young-Hoon Kim and Sanyogita Shamsunder, “Adaptive Algorithms for Channel Equalization with Soft Decision Feedback”, IEEE Journal on Selected Areas in Communications, vol. 16, No. 9, Dec. 1998, pp. 1660-1669.*
Stephen Oh and Domingo Garcia, “Implementation of a Parallel DFE using Residue Number System”, IEEE 1994, pp. III-237-III-240.*
Kalavai Ragunath and Keshab Parhi, “Parallel Adaptive Decision Feedback Equalizers,” IEEE Transactions on Signal Processing, vol. 41, No. 5, May 1993.
Danfeng Xu, Yonghua Song, Gregory T. Uehara, “TP4.7: A 200MHz 9-Tap Analog Equalizer for Magnetic Disk Read Channels in 0.6m CMOS,” ISSCC Digest of Technical Papers, pp. 74-75, Feb. 1996.
Azadet Kameran
Yu Ming-Lin
Agere Systems Guardian Corp.
Nguyen Dung X.
Pham Chi
Sofer & Haroun LLP
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