Boots – shoes – and leggings
Patent
1994-05-25
1995-08-15
Mai, Tan V.
Boots, shoes, and leggings
G06F 738
Patent
active
054425808
ABSTRACT:
A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.
REFERENCES:
patent: 5175702 (1992-12-01), Beraud et al.
patent: 5278781 (1994-01-01), Aono et al.
patent: 5297071 (1994-03-01), Sugino
patent: 5301340 (1994-04-01), Cook
Mai Tan V.
TCSI Corporation
Yin Ronald L.
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