Parallel processing based digital matched filter and error detec

Details Parallel processing based digital matched filter and error detec Parallel processing based digital matched filter and error detec

1993-12-28

1995-07-11

Swann, Tod R.

Pulse or digital communications

Repeaters

Testing

380 34, H04K 100

Patent

active

054328136

ABSTRACT:
A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches each having an analog to digital converter which converts a portion of an analog sample to digital format and effectively reduces the system clock rate by a ratio of the number of parallel branches. One set of parallel branches is coupled to an early-late clock error detector circuits and another set of parallel branches is coupled to data signal detector circuits and then combined before being applied to a clock error processing channel and a data signal phase error channel which maintains the lower clock rate of the parallel branches.

REFERENCES:
patent: 4841522 (1989-06-01), Yamazaki
patent: 5099494 (1992-03-01), Kingston et al.
patent: 5216691 (1993-06-01), Kaufmann
patent: 5253268 (1993-10-01), Omura et al.
patent: 5293398 (1994-03-01), Hamao et al.

Affiliated with

Also associated with

Rating

Parallel processing based digital matched filter and error detec does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel processing based digital matched filter and error detec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processing based digital matched filter and error detec will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-509216