Parallel processing architecture for video decompression

Details Parallel processing architecture for video decompression Parallel processing architecture for video decompression

2005-11-16

2011-10-04

Mehta, Bhavesh (Department: 2624)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C382S234000, C382S236000, C382S238000, C712S036000

Reexamination Certificate

active

08031772

ABSTRACT:
Disclosed herein is a video decoding system of a mobile broadcasting receiver. The video decoding system of a mobile broadcasting receiver for decoding a compression-coded video signal includes: at least one buffer memory for performing video decoding; a plurality of coprocessors including a data processing unit partitioned into one or more hardware blocks, wherein the data processing unit performs actual video decoding via data input/output from/to the buffer memory; and a DMA (Direct Memory Access) coprocessor for performing a direct access operation to an external memory, wherein, the at least one buffer memory, the plurality of coprocessors and the DMA coprocessor take the form of hardware, and operations thereof are controlled via software in a processor.

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