Parallel processing apparatus and method capable of switching pa

Details Parallel processing apparatus and method capable of switching pa Parallel processing apparatus and method capable of switching pa

1990-07-09

1994-02-15

Harrell, Robert B.

Undertaking

364DIG1, 3642281, 3642283, 364229, 3642302, G06F 900

Patent

active

052874656

ABSTRACT:
When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.

REFERENCES:
patent: 4942525 (1990-07-01), Shintani et al.
David J. Lilja "Reducing the Branch Penalty in Pipelined Processors.", Computer (Jul. 1988) pp. 47-55.
Miller et al. "Floating-Duplex Decode and Execution of Instruction.", IBM Technical Disclosure Bulletin, vol. 23, No. 1 (Jun. 1980) pp. 409-412.

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