Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-11-29
2002-10-29
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S141000, C341S144000, C341S155000, C341S118000
Reexamination Certificate
active
06473013
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method and apparatus for providing signal conversion, and more particularly to a parallel processing method and apparatus for converting signals between digital and analog.
BACKGROUND OF THE INVENTION
The performance of analog and digital converters is typically quantified by two primary parameters, speed (in samples per second) and resolution (in bits). Designers of analog and digital converters typically face the challenge of trading off the resolution of a converter with its speed.
One type of prior art, high-speed analog-to-digital converter, is implemented using M time-interleaved, moderate speed, analog-to-digital converters (ADCs) configured in an array. In a typical time-interleaved converter, the M ADCs comprising the converter are triggered successively at a rate equal to 1/M times the effective sample rate of the overall converter. One drawback of time-interleaved converters is limited speed and resolution due to the sensitivity of these converters to mismatches between characteristics (including gain, phase and DC offset) of the M ADCs and due to clock timing errors.
A block diagram of a second type of prior art converter
10
is shown in FIG.
1
. The converter
10
includes M analysis filters
12
A-
12
D, M synthesis filters
14
A-
14
D, M ADCs
16
A-
16
D, M downsamplers
18
A-
18
D, M upsamplers
20
A-
20
D and an adder
22
. The analysis filters
12
A-
12
D partition a wideband input signal, u[n], into M narrow subband signals, which are downsampled by a factor M in the downsamplers
16
A-
16
D. Each of the ADCs
16
A-
16
D converts one of the subband signals from analog to digital. The upsamplers
20
A-
20
D increase the sampling rate of the signals by a factor equal to M. The synthesis filters
14
A-
14
D in combination with the adder
22
reconstruct the input signal in digital format. The frequency response for typical filters used as the analysis filters
12
A-
12
D in the converter
10
are shown in FIG.
2
.
One advantage of the converter
10
over the typical time-interleaved converters discussed above is an improvement in speed and resolution that can be achieved due to an attenuation in the effects of gain and phase mismatches between ADCs in the array of ADCs. In one prior art converter, disclosed in U.S. Pat. No. 5,392,044 to Kotzin et al., that utilizes the architecture shown in
FIG. 1
, a fully discrete-time quadrature mirror filter (QMF) (e.g., utilizing switched-capacitors) is used to implement the analysis filters
12
A-
12
D. One drawback of this design is that the use of switched-capacitors limits the speed of the system and introduces switching noise which can limit the signal-to-noise ratio of the system. In addition, this converter is only capable of converting between discrete-time analog and discrete-time digital signals.
U.S. Pat. No. 5,568,142 to Velazquez et al., discloses a converter, having the architecture shown in
FIG. 1
, that overcomes some of the drawbacks of the converter disclosed by Kotzin et al. The converter disclosed by Velazquez et al. uses continuous-time analog analysis filters to feed each ADC in the converter and discrete-time digital synthesis filters to reconstruct the digitized signal. The primary drawbacks of this approach are that it uses high-order continuous-time analog filters with high stopband attenuation. Further, the converter disclosed in U.S. Pat. No. 5,568,142 is only capable of converting between continuous-time analog signals and discrete-time digital signals.
In addition to being concerned with the speed and resolution provided when selecting a converter architecture, designers of analog and digital converters are also typically concerned with the ease and accuracy of generating (or designing) and calibrating an analog and digital converter for a selected converter architecture. The ease and accuracy by which a specific analog and digital converter can be generated and calibrated is highly dependent on the architecture selected.
The discrete-time filter bank converter disclosed by Kotzin can be generated using standard digital filter bank generation techniques. However, disadvantages of these techniques are that round-off errors in implementing analog electronics in the converter can limit the resolution of the system, and the analog filters cannot typically be built with the same level of accuracy and precision of the digital filters, thereby limiting the performance of the system.
The converter disclosed by Velazquez et al. in U.S. Pat. No. 5,568,142 can be generated, as described in the patent, using an iterative optimization of the continuous-time filters followed by an iterative optimization of the discrete-time filters. The primary disadvantage of this approach is that it can be computationally intensive and is not guaranteed to converge to an accurate result.
Many prior art converters and other electronic systems are calibrated for peak performance by injecting a known test signal, measuring performance, and adjusting the electronics to correct for errors. Wideband pseudorandom signals have been used as calibration signal sources for electronic systems. The primary disadvantage of this calibration technique is that it can mask the magnitude and sources of individual errors and make it difficult to isolate and correct the individual errors.
The converter disclosed by Velazquez et al. in U.S. Pat. No. 5,568,142 can be calibrated, as described in the patent, by measuring the performance of subband signals followed by an iterative optimization of the digital filters to compensate for any errors detected. The primary disadvantages of this technique are that it is hardware intensive (since it requires measurement of each of the M subband signals), computationally complex and not guaranteed to converge to an accurate result.
It is desirable to provide an analog and digital converter that overcomes the drawbacks of the prior art discussed above.
SUMMARY OF THE INVENTION
Embodiments of the present invention are directed to methods and apparatus for providing analog and digital conversion that overcome drawbacks of the prior art discussed above. It should be noted that the term “analog and digital converter” as used herein includes analog-to-digital converters and digital-to-analog converters.
In one general aspect, the invention features a converter for converting an input signal from a first format to a second format. The converter includes a decomposition section, a converter array operatively coupled to the decomposition section, and a recombination section operatively coupled to the converter array. The decomposition section includes an input to receive the input signal, a splitter to divide the input signal into a plurality of signals, a plurality of signal outputs, each of which provides as an output one of the plurality of signals, and a clock circuit having a plurality of clock outputs for providing sample clocks to the converter array. The converter array includes a plurality of converters, each of the converters having a signal input to receive one of the plurality of signals, a clock input to receive one of the sample clocks and an output that provides a converted signal. At least one of the decomposition section and the recombination section includes filters for filtering either the plurality of signals or the plurality of converted signals.
The first format of the converter system can be analog, the second format can be digital, each of the converters of the converter array can be an analog to digital converter, and the recombination section can include a plurality of filters for filtering each of the converted signals. The clock circuit can be constructed and arranged to introduce a phase delay in at least one of the sample clocks The decomposition section can be constructed and arranged to receive as the input signal at least one of a continuous-time analog signal and a discrete-time analog signal. The recombination section can include a plurality of outputs that provide a plurality of converter output sig
Velazquez Richard J.
Velazquez Scott R.
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