Parallel prefix networks that make tradeoffs between logic...

Details Parallel prefix networks that make tradeoffs between logic... Parallel prefix networks that make tradeoffs between logic...

2006-12-19

2006-12-19

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07152089

ABSTRACT:
A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X1} using an associative two-input operator ∘, such that, Y1=X1, Y2=X2∘X1, Y3=X3∘X2∘X1, . . . , and YN=XN∘XN−1∘ . . . ∘X2∘X1. Within this prefix network, each prefix cell has a fanout of at most 2f+1, and there are at most 2thorizontal wiring tracks between each logic level. Additionally, l+f+t=L−1, and unlike existing prefix circuits, 1>0,f>0, and t>0.

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