Patent
1993-01-12
1995-02-21
Jankos, Almis
395163, 395143, G06F 1562
Patent
active
053923928
ABSTRACT:
A parallel polygon/pixel rendering engine for a digital map capable of producing real-time linear shaded, three dimensional, raster graphics for video generation. The apparatus is suitable for use with avionic display systems, particularly digital map displays which include an instruction and interpreter unit and an image scanner. The apparatus comprises a raster engine, a memory interface and a bit mapped memory. The raster engine further includes a raster engine control and generic interpolation polygon processor interface, an edge interpolator, a line interpolator and a controller for the edge and line interpolators. The raster engine control is electrically connected to receive data from the instruction interface unit and is further electrically connected to the edge interpolator and interpolator controller. The edge interpolator is adapted to receive data from the raster engine control and the line interpolator is electrically connected to receive data from the edge interpolator. A first edge pipeline is connected to a second output of the raster engineer control and a second edge pipeline is connected to an output of the first edge pipeline as well as an output of the edge interpolator. An output from the second stage of the edge pipeline and a plurality of outputs from the line interpolators are then fed to a memory interface which is connected to receive data from the plurality of outputs. A bit mapped memory is also connected to receive data from the memory interface and control signals from a bit mapped memory controller. The bit map memory controller controls the memory interface components and the bit map memory during both normal and test modes.
REFERENCES:
patent: 4862391 (1989-08-01), Ohhashi
patent: 4924414 (1990-05-01), Ueda
patent: 4949280 (1990-08-01), Littlefield
patent: 4974177 (1990-11-01), Nishiguchi
patent: 5060172 (1991-10-01), Engelse et al.
patent: 5088053 (1992-02-01), Sprague et al.
Ohhashi, Masahide, Nobuyuki Ikumi, Satoshi Itoh, "A 32B 3-D Graphic Processor Chip With 10M Pixels/s Gouraud Shading", Session XII: Video and Graphics Signal processors, IEEE International Solid State Circuits Conference, vol. 31, 17 Feb. 1988, New York, pp. 168-169.
Fischer Douglas A.
Graves Jennifer A.
Snodgrass Thomas D.
Champion Ronald E.
Honeywell Inc.
Jankos Almis
Lervick Craig J.
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