Boots – shoes – and leggings
Patent
1989-03-28
1989-10-24
Shaw, Gareth D.
Boots, shoes, and leggings
3642443, 3642545, 3642318, G06F 928, G06F 938
Patent
active
048766445
ABSTRACT:
A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when the neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.
REFERENCES:
patent: 4395698 (1983-07-01), Sternberg et al.
patent: 4550437 (1985-10-01), Kobayashi et al.
patent: 4594660 (1986-06-01), Guenthner et al.
patent: 4649512 (1987-03-01), Nukiyama
Nuechterlein David W.
Rinaldi Mark A.
Fairbanks Jonathan C.
Frisone John B.
International Business Machines Corp.
Shaw Gareth D.
LandOfFree
Parallel pipelined processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel pipelined processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel pipelined processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1592639