Data processing: speech signal processing – linguistics – language – Speech signal processing – For storage or transmission
Reexamination Certificate
1999-03-16
2001-11-06
Korzuch, William (Department: 2641)
Data processing: speech signal processing, linguistics, language
Speech signal processing
For storage or transmission
C701S222000, C701S216000, C701S200000, C370S216000, C370S535000, C375S240220, C375S240120
Reexamination Certificate
active
06314393
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to speech signal processing and, more particularly, to processors designed to implement codebook-excited linear prediction (CELP) speech coding and decoding.
2. Description of the Related Art
Speech signal encoding lowers the number of bits required to transmit an accurate digital representation of a speech signal. Lowering the bit rate without decreasing the data transmission rate, in turn, advantageously allows the number of speech signals transmitted within a given bandwidth to be increased. A lower bit rate may also provide better error protection. One particular encoding scheme, codebook-excited linear prediction (CELP) coding, has been used to lower the bit rate from 64 Kbit/sec (the rate at which standard pulse-code modulated speech is transmitted) to as low as 4.0 Kbit/sec. CELP coders are a class of analysis-by-synthesis coders. That is, the coding algorithm chooses coding parameters by reconstructing the speech signal from the potential coding parameters. As a result, a CELP coder performs the same algorithms utilized by a CELP decoder to determine which encoded signal is optimal.
In a low-delay CELP system (LD-CELP) such as the one set forth in CCITT Recommendation G.728, “Coding of Speech at 16 kbit/s Using Low-Delay Code Excited Linear Prediction” (Geneva, September, 1992), the reconstructed speech signal is synthesized by filtering an excitation signal through a synthesis filter constructed from short-term prediction coefficients. The excitation signal is derived from a gain-scaled contribution from a fixed codebook, which contains a set of excitation vectors that are characteristic of the speech signal being encoded.
The optimal codebook indices and gain coefficients are typically determined through the analysis-by-synthesis procedure. More particularly, each codebook vector may be evaluated to determine the vector and gain parameters that minimize the error between the synthesized signal and the actual speech signal.
Because each codebook entry must be evaluated for each speech segment, prior methods of implementing the CELP coder (and corresponding decoder) have required a high-performance, general-purpose digital signal processor (DSP). This general purpose DSP must also be capable of determining the optimum codebook vectors and gain parameters in real-time. Adequate general purpose DSPs, however, have been found to be undesirably expensive.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, an integrated circuit is useful for processing a speech signal in accordance with a CELP standard. The circuit includes a data bus, a plurality of processing elements coupled to the data bus in parallel, and an auxiliary processing element coupled to the data bus. Each processing element includes a multiplier and an accumulator, while the auxiliary processing element has a division unit and a comparator. The plurality of processing elements and the auxiliary processing element are also coupled in a pipeline formation.
In accordance with another aspect of the present invention, a speech coder that implements a CELP standard to code a speech signal includes a data bus, a first memory coupled to the data bus and storing quantized speech vectors, and a plurality of processing elements that operate on the quantized speech vectors and the speech signal. Each processing element of the plurality of processing elements is coupled to the data bus, and adjacent processing elements are coupled in a pipeline formation. The plurality of processing elements includes multiple multiply-accumulate processing elements and an auxiliary processing element having a division unit and a comparator. The speech coder further includes a second memory coupled to the auxiliary processing element and storing constant values utilized by the comparator of the auxiliary processing element.
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Patel Shvetal K.
Swaminathan Kumar
Zheng Yue-Peng
Chawan Vijay B
Hughes Electronics Corporation
Korzuch William
Sales Michael W.
Whelan John T.
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