Parallel phase locked loops skew measure and dynamic skew...

Details Parallel phase locked loops skew measure and dynamic skew... Parallel phase locked loops skew measure and dynamic skew...

1999-12-30

2002-10-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000

Reexamination Certificate

active

06469550

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to synchronizing circuits that use phase locked loops (PLLs) and in particular, to dynamic skew compensation in PLLs.
BACKGROUND OF THE INVENTION
Synchronous circuits such as synchronous integrated circuits, generally require clock generators that synthesize desired frequencies and are in sync with a reference clock. In many instances, the clock generator may be a PLL circuit. However, between two or more circuits with two or more PLLs, the operational frequency of one circuit may be different from the other. Moreover, the frequency of one circuit may not be a multiple of the other. In this instance, a PLL is used to synthesize a frequency for use by a respective circuit. For example, each circuit uses a PLL to synthesize a frequency from a reference clock (XCLK). One PLL may synthesize a frequency of XCLK *N and another PLL may synthesize a frequency of XCLK *M, where N and M are real numbers.
In instances where signals need to interface between two or more PLL clock domains, the skew and jitter of each PLL utilized needs to be accounted for so there can be synchronous transmission of signals without errors. However, between PLL clock domains operating at high frequencies, skew and jitter make it difficult for such signals to be transmitted synchronously without synchronization mechanisms. However, to add a synchronization mechanism to every signal that crosses the boundary between two PLL clock domains is costly in terms of power, substrate area and signal latencies. Therefore, it is desired to allow a signal to cross between PLL clock domains with minimum signal latencies and to save power and substrate area, without requiring synchronization mechanisms.
SUMMARY
An apparatus and method are disclosed in which a plurality of programmable delay lines corresponding to a plurality of signals are provided such that each delay line is in a path of a corresponding signal. A skew measure circuit is configured to receive at least two signals to be synced and determine a phase difference between the at least two signals. The skew measure circuit is coupled to the plurality of delay lines, and the skew measure circuit is further configured to use the phase difference to program at least one of the delay lines to delay at least one of the signals to be synced such that the signals are in sync.
Additional features, embodiments, and benefits will be evident in view of the figures and detailed description presented herein.


REFERENCES:
patent: 5627500 (1997-05-01), Wolaver et al.
patent: 5631591 (1997-05-01), Bar-Niv
patent: 5675273 (1997-10-01), Masleid
patent: 5819076 (1998-10-01), Jeddeloh et al.
patent: 5990719 (1999-11-01), Dai et al.

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