Parallel page buffer verify or read of cells on a word line usin

Details Parallel page buffer verify or read of cells on a word line usin Parallel page buffer verify or read of cells on a word line usin

1996-04-05

1997-06-10

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518905, 365210, 36518909, G11C 700

Patent

active

056383266

ABSTRACT:
A flash memory including a page buffer with bias circuitry and a reference array enabling reading and verifying values stored on a word line of memory cells in parallel using the page buffer irrespective of temperature, Vcc, and process variations. The bias circuitry includes a cascode transistor having a source connected to the reference cell array which provides a single reference signal. The bias cascode couples the reference signal to an input of a bias inverter in the bias generator, while a bias load transistor in the bias generator couples Vcc to the bias inverter input. The page buffer includes a set of latches that are each coupled to a memory cell by a cascode. A first inverter in each latch has transistors with sizes matching the transistors in the bias inverter. A latch load transistor is connected between a pull-up and pull-down transistor of a second inverter in each latch and is sized to match the bias load transistor. Gates of the bias load transistor and the latch load transistor are both coupled to the output of the bias inverter enabling the first inverter of each latch to have an input mirroring the input of the bias inverter.

REFERENCES:
patent: 5197028 (1993-03-01), Nakai
patent: 5363340 (1994-11-01), Ishikawa et al.
patent: 5559737 (1996-11-01), Tanaka et al.
Kobayashi, et al., ULSI Laboratory, Mitsubishi Electric Corporation, Itami Japan, A 3.3 v Only 16 Mb DINOR Flash Memory.

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