Parallel output architectures for CMOS active pixel sensors

Details Parallel output architectures for CMOS active pixel sensors Parallel output architectures for CMOS active pixel sensors

1998-06-22

2002-10-15

Ho, Tuan (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

Reexamination Certificate

active

06466265

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to solid state imager sensors having multiple output channels, and more particularly to architectures based on CMOS active pixel sensors (APS) having multiple output channels that are designed for image capture requiring high frame and pixel rates. It is also applicable to systems where it is desirable to have separate output channels for each of the color defined by a mosaic Color Filter Array (CFA). The architecture is also suitable to other types of x-y addressable imaging array.
BACKGROUND OF THE INVENTION
The prior art has taught image sensors that have requirements to output data at a high pixel data rate. Typically, these high pixel rate requirements are achieved by employing a two-dimensional array (an x-y array) of pixels arranged into two split fields such that the output of one half of the pixels are sent to signal processing circuits located at an edge of the array adjacent to that half. The other half the pixels are output to similar circuits located adjacent to that half. Technologies that can be used to implement such arrays in the prior art have been CMOS APS or CCD. Other prior art teachings have disclosed two-dimensional arrays that are formed into many blocks that each having their own output paths. These multiple output path prior art devices have increased the output data rate for image sensor arrays, however, they are limited in the amount and types of versatility that they provide.
In a conventional CMOS APS, only a single row of the pixel array is addressed and the image data from that row is transferred in parallel to column circuits for signal processing such as offset removal. Each pixel in a selected row is read out in sequence to form one line of output image data. The total number of pixels in the array and the frame rate determine the pixel output rate. For high frame-rate devices or devices having a large pixel count for image capture, the enough to capture and deliver the signal with high fidelity to the image digitization and store unit. For example, a 1000×1000 (megapixel) array running at 30 frames/second has a pixel output rate of over 30 MHz. However, a 500×500 pixel array running at 1000 frames/sec requires in excess of 250 MHz output data rate. Typical state-of-the-art pixel data channels (both the analog signal and the digitization circuits) are only capable pixel transfer rates in the of 10's of MHz range, and therefore multiple parallel output channels are necessary to achieve high pixel output rate for high frame rate and high pixels count sensors.
From the foregoing discussion, it should be apparent that there remains a need within the art for a more versatile multiple array for achieving high pixel rate data transfers.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problems in the prior art by providing a CMOS based architecture for active pixel sensors (APS). A semiconductor substrate having a two dimensional array of pixels arranged in a plurality of rows and columns is provided with a row addressing circuit formed on the substrate, a column addressing circuit formed on the substrate, a plurality of signal processing circuits operatively connected to the array of pixels such that each of the signal processing circuits is electrically connected to a predetermined subset of pixels within the array through electrically conductive signal busses, wherein each of the subsets comprises a plurality of pixels, and means for employing the row addressing circuit and the column addressing circuit to select a sequence of pixels having one pixel for each of the subsets and simultaneously transferring signals from each of the pixel sequences to the signal processing circuits.
ADVANTAGEOUS EFFECT OF THE INVENTION
The present invention in providing a CMOS based architecture that is fully compatible with the APS characteristics yields numerous advantages: it provides x-y addressability; sub-windowing and sub-sampling of the pixel array (to provide for example a higher frame rate with fewer pixels per frame); for color image sensors having mosaic Color Filter Arrays it provides a parallel channel connection scheme can be used to preserve the CFA pattern during sub-sampling; and for CFA-based color image sensors, each of the parallel channels can be used for a single color to simplify color signal processing (such as color-specific gain setting and digitization).


REFERENCES:
patent: 4541010 (1985-09-01), Alston
patent: 5434619 (1995-07-01), Yonemoto
patent: 5790191 (1998-08-01), Zhang
patent: 5953060 (1999-09-01), Dierickx

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