Parallel operation processor utilizing SIMD data transfers

Details Parallel operation processor utilizing SIMD data transfers Parallel operation processor utilizing SIMD data transfers

2005-02-09

2008-08-12

Dollinger, Tonia L. M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S225000

Reexamination Certificate

active

07412587

ABSTRACT:
A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.

REFERENCES:
patent: 5581773 (1996-12-01), Glover
patent: 5825921 (1998-10-01), Dulong
patent: 5913041 (1999-06-01), Ramanathan et al.
patent: 7065590 (2006-06-01), Kitagawa
patent: 2002/0029208 (2002-03-01), Josephson

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