Pulse or digital communications – Repeaters – Testing
Patent
1994-07-01
1997-04-29
An, Meng-Ai
Pulse or digital communications
Repeaters
Testing
375261, 375265, 3649194, 3649278, 36492792, 364929, 3649314, 3649328, 3649428, 3649462, 364DIG2, G06F 1300, G06F 1516
Patent
active
056258283
ABSTRACT:
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. The system executes a novel QAM.backslash.TCM modem algorithm.
REFERENCES:
patent: 4520490 (1985-05-01), Wei
patent: 4534040 (1985-08-01), Thadar
patent: 4594651 (1986-06-01), Jaswa et al.
patent: 4641238 (1987-02-01), Kneib
patent: 4799144 (1989-01-01), Parruck et al.
patent: 4860191 (1989-08-01), Nomura et al.
patent: 4873701 (1989-10-01), Tretter
patent: 4991169 (1991-02-01), Davis et al.
patent: 5029204 (1991-07-01), Shenoi et al.
patent: 5031195 (1991-07-01), Chevillat et al.
patent: 5036539 (1991-07-01), Wrench, Jr. et al.
patent: 5105442 (1992-04-01), Wei
patent: 5111530 (1992-05-01), Kutaragi et al.
patent: 5200981 (1993-04-01), Carmon
patent: 5208832 (1993-05-01), Greiss
patent: 5245632 (1993-09-01), Greiss et al.
patent: 5291614 (1994-03-01), Baker et al.
patent: 5293586 (1994-03-01), Yamazaki et al.
patent: 5305352 (1994-04-01), Calderbank et al.
patent: 5388124 (1995-02-01), Laroia et al.
patent: 5418798 (1995-05-01), Wei
Ruby B. Lee, "HP Precision: A Spectrum Architecture"; Hewlett Packard Co. IEEE 1989, pp. 242-251.
Fotland; David; "Hardware Design of the First HP Precision Architecture Computers" Hewlett Packard Journal, Mar. 1987, pp. 4-17.
Ohad Falik et al; "NSC's Digital Answering Machines Solution"; IEEE 1992 pp. 132-137.
Hanoch et al; "Functional Design Verification of the NS32FX16"; May 3, 1991 IEEE.
"A pipelined interface for high floating-point performance with precise exceptions"; IEEE Jun. 1988, pp. 77-87; Sorin IcCA BoVici.
"Application Specific Microprocessor"; IEEE 1990, pp. 351-354, Intrater et al.
"Architecture Considerations for SF-Core Based Microprocessor"; IEEE 1991 pp. 21-23, Shacham et al.
"High performance tax processor"; by National Semiconductor NSFX 16-15/NS 32 FX 16; pp. 1-84, 1990.
Carmon Iddo
Cohen Ronny
Fraenkel Itael
Viner Omri
An Meng-Ai
National Semiconductor Corporation
LandOfFree
Parallel operating CPU core and DSP module for executing sequenc does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel operating CPU core and DSP module for executing sequenc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel operating CPU core and DSP module for executing sequenc will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-714760