Data processing: database and file management or data structures – Data integrity – Transactional processing
Reexamination Certificate
2011-06-14
2011-06-14
Corrielus, Jean M (Department: 2162)
Data processing: database and file management or data structures
Data integrity
Transactional processing
C707S678000, C707S679000, C707S680000, C707S682000, C707S684000, C707S704000, C707S692000, C707S674000, C707S609000
Reexamination Certificate
active
07962456
ABSTRACT:
Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. For example, pessimistic reads are supported. A pessimistic duplication detection data structure is created for a parallel nested transaction. An entry is made into the data structure for each pessimistic read in the parallel nested transaction. When committing the parallel nested transaction, new pessimistic read locks are passed to an immediate parent, and an entry is made into a separate pessimistic duplication detection data structure of the immediate parent with synchronization between sibling transactions. The pessimistic duplication detection data structures can also be used for upgrades from pessimistic reads to write locks. Retry operations are supported with parallel nested transactions. Write abort compensation maps can be used with parallel nested transactions to detect and handle falsely doomed parent transactions.
REFERENCES:
patent: 5251318 (1993-10-01), Nitta et al.
patent: 5263155 (1993-11-01), Wang
patent: 5687363 (1997-11-01), Oulid-Aissa et al.
patent: 5721909 (1998-02-01), Oulid-Aissa et al.
patent: 5764977 (1998-06-01), Oulid-Aissa et al.
patent: 5835757 (1998-11-01), Oulid-Aissa et al.
patent: 5983225 (1999-11-01), Anfindsen
patent: 6052695 (2000-04-01), Abe et al.
patent: 6295610 (2001-09-01), Ganesh et al.
patent: 6343339 (2002-01-01), Daynes
patent: 6578033 (2003-06-01), Singhal et al.
patent: 6772154 (2004-08-01), Daynes et al.
patent: 6772255 (2004-08-01), Daynes
patent: 6990503 (2006-01-01), Luo et al.
patent: 7234076 (2007-06-01), Daynes et al.
patent: 7289992 (2007-10-01), Walker
patent: 7418706 (2008-08-01), Luo et al.
patent: 7478210 (2009-01-01), Saha et al.
patent: 7496574 (2009-02-01), Walker
patent: 7516366 (2009-04-01), Lev et al.
patent: 7650371 (2010-01-01), Duffy et al.
patent: 7840530 (2010-11-01), Magruder et al.
patent: 2007/0136365 (2007-06-01), Tarditi, Jr. et al.
patent: 2007/0162520 (2007-07-01), Petersen et al.
patent: 2007/0198519 (2007-08-01), Dice et al.
patent: 2007/0198978 (2007-08-01), Dice et al.
patent: 2008/0147757 (2008-06-01), Duffy et al.
patent: 2009/0006407 (2009-01-01), Magruder et al.
patent: 2009/0077082 (2009-03-01), Magruder et al.
patent: 2009/0077083 (2009-03-01), Magruder et al.
Agrawal, Kunal, et al., “Nested Parallelism in Transactional Memory,” The Second ACM SIGPLAN Workshop on Transactional Computing, pp. 1-12 (Aug. 16, 2007).
Dice, Dave, et al., “What Really Makes Transactions Faster?,” First ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, pp. 11 (Jun. 2006).
Dice, Dave, et al., “Transactional Locking II,” Lecture Notes in Computer Science, vol. 4167 pp. 194-208 (Sep. 2006).
Moss, J. Eliot, et al., “Nested Transactional Memory: Model and Architecture Sketches,” Science of Computer Programming, vol. 2, No. 63, pp. 1-16 (2006).
The Office Action for U.S. Appl. No. 11/901,494 mailed Nov. 16, 2009 (9 pages).
The Notice of Allowance for U.S. Appl. No. 11/901,494 mailed Mar. 29, 2010 (16 pages).
The Office Action for U.S. Appl. No. 11/901,647 mailed Nov. 16, 2009 (10 pages).
The Final Office Action for U.S. Appl. No. 11/901,647 mailed May 14, 2010 (9 pages).
The Written Opinion of the International Searching Authority for International Application No. PCT/ US2008/076563 mailed Mar. 18, 2009 (4 pages).
The International Search Report for International Application No. PCT/US2008/076563 mailed Mar. 18, 2009 (3 pages).
The Written Opinion of the International Searching Authority for International Application No. PCT/ US2008/076564 mailed Mar. 31, 2009 (3 pages).
The International Search Report for International Application No. PCT/US2008/076564 mailed Mar. 31, 2009 (2 pages).
The Notice of Allowance for U.S. Appl. No. 11/901,647 mailed Oct. 7, 2010 (14 pages).
McDonald, Austen, et al., “Architectural Semantics for Practical Transactional Memory,” Proceedings of the 33rd Annual International Symposium on Computer Architecture, pp. 12 (2006).
Moravan, Michelle, J. et al., “Supporting Nested Transactional Memory in LogTM,” Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 1-12 (Oct. 21-25, 2006).
The Written Opinion of the International Searching Authority for International Application No. PCT/ US2008/076565 mailed Mar. 18, 2009 (3 pages).
The International Search Report for International Application No. PCT/US2008/076565 mailed Mar. 18, 2009 (3 pages).
Detlefs David
Duffy John Joseph
Graefe Goetz
Grover Vinod K.
Magruder Michael M.
Corrielus Jean M
Microsoft Corporation
LandOfFree
Parallel nested transactions in transactional memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel nested transactions in transactional memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel nested transactions in transactional memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2654566