Boots – shoes – and leggings
Patent
1985-05-02
1988-05-31
Malzahn, David H.
Boots, shoes, and leggings
G06F 752
Patent
active
047485841
ABSTRACT:
The basic cells of a parallel multiplier are arranged into arrays corresponding in number to the number of bits of multiplier data Y and multiplicand data X. Multiplicand data supply lines supply bit data Xi corresponding to the basic cell of the multiplicand data X, its inverted data Xi, bit data Xi-1 one digit lower than said corresponding bit, and its inverted data Xi-1 to each of the basic cells. Decoders decode multiplier data Y based on the Booth's algorithm. These decoders supply a prescribed select signal to the basic cells. The basic cells comprise a selecting circuit for selectively inputting one of data Xi, Xi, Xi-1, Xi-1 and "0" according to the select signal from the decoders, and a full adder. The full adder receives the data input by the selecting circuit as the augend data and receives the addend and carry data from the previous row of basic cells. The full adder adds the augend, addend and carry data, and outputs sum and carry data.
REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4168530 (1979-09-01), Gajski et al.
patent: 4575812 (1986-03-01), Kloker et al.
Japanese Patent Publication (KOKOKU), No. 57-28129.
Review on a Multiplier Circuit System Using a Parallel Operation System of a Now Progressing LSI Version, Nikkei Electronics; pp. 76-89, esp. p. 84, May 29, 1978.
Kabushiki Kaisha Toshiba
Malzahn David H.
LandOfFree
Parallel multiplier utilizing Booth's algorithm does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel multiplier utilizing Booth's algorithm, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel multiplier utilizing Booth's algorithm will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1878631