Parallel multiplier using skip array and modified wallace tree

Details Parallel multiplier using skip array and modified wallace tree Parallel multiplier using skip array and modified wallace tree

1991-01-04

1993-01-19

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

051811855

ABSTRACT:
A parallel multiplier by a skip array and a modified Wallace tree utilizes a modified Booth's encoder for encoding a multiplier according to a modified Booth's algorithm, a skip array for partial products, a modified wallace tree for adding binary bits, and a hybrid prefix adder for adding the final two lines. Fast multiplication of 0 (log n) is continuously performed without a standby state of a carry output and the regularity of the arrangement of the parallel multiplier is improved so that its chip area and manufacturing cost are reduced.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4556948 (1985-12-01), Mercy
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4918639 (1990-04-01), Schwarz et al.
patent: 4999804 (1991-03-01), Nukiyama

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