Boots – shoes – and leggings
Patent
1991-02-12
1991-10-22
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 752
Patent
active
050601830
ABSTRACT:
A parallel multiplier utilizing arrays of logic cells. A first circuit logic array forms and sums partial products of the most significant bits of the multiplicand with the multiplier. A second logic array forms and sums partial products of the least significant bits of the multiplier. A third circuit logic array which adds results of the partial product addition performed in parallel by the first and second circuit logic arrays. Since the first and second logic groups execute, respectively, the partial product addition in parallel, the number of adding steps is reduced as a whole and the operation speed is improved. The third logic array is disposed between the first and second logic arrays, resulting in a reasonable structure for circuit integrations and further improving system speed.
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"A CMOS/SOS Multiplier," Iwamura et al., International Solid-State Circuit Conference, 1984.
Sakashita Kazuhiro
Tsujihashi Yoshiki
Harkcom Gary V.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Long T.
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