Parallel multiplier array with foreshortened sign extension

Details Parallel multiplier array with foreshortened sign extension Parallel multiplier array with foreshortened sign extension

1985-06-19

1988-05-31

Harkcom, Gary V.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

047485825

ABSTRACT:
A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.

REFERENCES:
patent: 3878985 (1975-04-01), Ghest et al.
patent: 4546446 (1985-10-01), Machida
patent: 4644488 (1987-02-01), Nathan
S. Bandyopadhyay et al., "An Iterative Array for Multiplication of Signed Binary Numbers", IEEE Trans. on Computers, Aug. 1972, pp. 921-922.

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