Parallel multiplier

Details Parallel multiplier Parallel multiplier

1998-09-09

2001-07-17

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C327S408000

Reexamination Certificate

active

06263357

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiplier, and in particular, to a parallel multiplier, in which, for example, used as a multiplier block in a digital signal processor or a video data converter.
2. Background of the Related Art
In general, a multiplier comprises a plurality of basic cells having adders which are arranged in a two-dimensional plane.
FIG. 1
is a block diagram showing a related art array multiplier using the basic cells. Cells C
00
-C
33
have a matrix structure, and are supplied 4-bit multiplicand data a
0
-a
3
and 4-bit multiplier data b
0
-b
3
to produce 8-bit product data.
FIG. 2
is the detailed circuit of basic cells in
FIG. 1. A
basic cell Cij transfers input data ai and bj to the next stage and add the two data to output a carry-out signal and a sum-out signal. ai and bj are applied a 1-bit multiplicand and a 1-bit multiplier, respectively. At this time, each input terminal of the sum-in and the carry-in of the cell C
00
is applied the initial value
0
. Referring to
FIG. 1
, the detailed operation of the related art array multiplier will be described as followings.
Cell C
00
is applied a
0
, b
0
and 0 as the initial value of a carry-in and a sum-in signal, respectively, and outputs a carry-out signal and a sum-out signal. C
01
is applied a
0
and the carry-out signal from C
00
and C
10
is applied a 1, 0 of the carry-in initial value, the sum-out signal from C
01
and b
0
to conduct an arithmetic operation. The other cells operate as aforementioned. The sum-out signals of cells C
00
, C
10
, C
20
, C
30
located at the right end column produce the product data P
0
-P
3
. Also, the sum-out signals of cells C
30
, C
31
, C
32
, C
33
located at the bottom row produce the product data P
4
-P
7
. That is, the related art array multiplier of
FIG. 1
comprises a plurality of basic cells arranged in a two-dimensional plane and multiplies 4-bit binary multiplicand data a
0
-a
3
by 4-bit binary multiplier data b
0
-b
3
to produce 8-bit binary product data P
0
-P
7
.
The related art array multiplier uses a plurality of basic cells arranged in a two-dimensional plane and conducts ten steps of arithmetic operation. Therefore, there is a problem in the operating speed.
In order to solve the problem,
FIGS. 3 and 4
show another related art array multiplier. The pipelined array multiplier of
FIG. 3
has a register
10
, and obtains a higher speed of operation than the multiplier of
FIG. 1
by reducing the operating steps. However, due to the inserted register, the structure is more complex than the array multiplier of
FIG. 1
, and the required area is increased. Also, the pipelined array multiplier of
FIG. 4
has two registers
11
and
12
and a carry propagate adder
40
, and it is difficult to obtain a simple and high-integrated circuit. The cells in
FIGS. 3 and 4
have the same structure as those in FIG.
1
.
The publication “The Design And Analysis Of VLSI Circuits”, which is published by Lance A. Glasser and Daniel W. Dobberpuhl, pages 52-55 describes the related art array multipliers of
FIGS. 1
,
3
and
4
in detail.
As described above, the related art array multipliers comprise a plurality of basic cell arranged in a two-dimensional plane and conduct a multi-step arithmetic operation, thereby having a problem that the operating speed is delayed. Also, registers may be used for a high-speed operation. But it makes the circuit complex and the required area increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a parallel multiplier that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a parallel multiplier which has a simple structure.
A further object of the present invention is to provide a parallel multiplier which can a high degree of integration.
A further object of the present invention is to provide a parallel multiplier which can operates with high speed.
In order to achieve at least the above object in a whole or in parts, a parallel multiplier is provided according to the present invention that includes a plurality of selector being applied a multiplicand and each 1 bit data of a multiplier to selectively output the multiplicand or 0 according to said 1 bit data of the multiplier; and a plurality of adders being applied output data from said selector to output a product by adding two neighboring output data from selector after 1 bit downshifting the lower bit output data.
To further achieve the above objects in a whole or in parts, there is provided a parallel multiplier according to the present invention that includes m multiplexers being applied an n bit multiplicand and n bit
0
through select-input terminals and each 1 bit data of a m bit multiplier through a select terminal to selectively output said n bit multiplicand if said 1 bit data is 1 or n bit
0
if 0; and a plurality of adders being applied said n bit output data from said multiplexers to output an n+m bit product by adding two neighboring output data from said multiplexers after 1 bit downshifting the lower bit output data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5233233 (1993-08-01), Inoue et al.
patent: 5465226 (1995-11-01), Goto
patent: 5784011 (1998-07-01), Malladi
patent: 5805477 (1998-09-01), Perner
patent: 5974437 (1999-10-01), Johannsen

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