Parallel multiplication logic circuit

Details Parallel multiplication logic circuit Parallel multiplication logic circuit

1995-07-12

1998-04-14

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

057400954

ABSTRACT:
A multiplication circuit having a Booth decoder, a partial product generator and a computation and formatting circuit. An incrementing device is combined with the computation circuit, enabling an anticipated incrementation if it is desired to obtain a rounded result.

REFERENCES:
patent: 5253195 (1993-10-01), Broker et al.
patent: 5465226 (1995-11-01), Goto
Richard, et al., "Fast-LSI, A Second Generation Advanced Schottky Technology," Electro 84. Electronic Show and Convention, Boston, MA, pp. 9/1/1-9 (1984).
Goto, et al., "A 54.times.54-b Regularly Structured Tree Multiplier," IEEE Journal of Solid-State Circuits, vol. 27, No. 9, p. 1229 (1992).

Affiliated with

Also associated with

Rating

Parallel multiplication logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel multiplication logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel multiplication logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-642639