Parallel multiplexing duty cycle adjustment circuit with...

Details Parallel multiplexing duty cycle adjustment circuit with... Parallel multiplexing duty cycle adjustment circuit with...

2007-05-01

2009-06-09

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000

Reexamination Certificate

active

07545190

ABSTRACT:
A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.

REFERENCES:
patent: 6593789 (2003-07-01), Atallah et al.
patent: 6806752 (2004-10-01), Heyne
patent: 6831493 (2004-12-01), Ma
patent: 6933759 (2005-08-01), Wu et al.
patent: 7113053 (2006-09-01), Yoshikawa
patent: 7180346 (2007-02-01), Lee
patent: 7202722 (2007-04-01), Mahadevan et al.

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