Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-03-09
2004-05-18
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C712S224000
Reexamination Certificate
active
06738792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of digital devices and, more particularly, to mask generators.
2. Description of the Related Art
Mask generators have a wide variety of uses in digital devices. For example, in processors, mask generators are used to generate masks to identify valid instruction bytes fetched from an instruction cache (e.g. the bytes in the cache line which are subsequent to the fetch address offset with the cache line or prior to a predicted-taken branch within the cache line), to identify cache memory array columns which are selected for use (e.g. programming the redundant columns in the array), etc.
In the past, mask generators which generate masks having a single transition between a binary one and a binary zero (e.g. a set of consecutive binary ones on one side of the transition point and a set of consecutive binary zeros on the other side of the transition point, such as 0011 or 1110 for a four bit mask) have been simple ripple designs. Generally, such a mask generator receives a pointer indicating the location of the transition within the mask. The pointer is decoded to generate a set of output bits corresponding to each mask bit, with the bit corresponding to the location indicated by the pointer being set and the other bits being clear (or vice versa). A particular mask bit is then generated as a logical OR of the decoder bits corresponding to all less significant mask bits than that particular mask bit. While such a circuit may be useful for small masks, generating wider masks in this fashion leads to large and slow circuits for performing the wide OR functions.
Another type of mask generator is described in U.S. Pat. No. 5,935,239, incorporated herein by reference in its entirety. The mask generator in this patent generates a mask from the least significant bits of the pointer and provides the mask to a set of multiplexors which also receive a range of all binary zeros and all binary ones. Each of the multiplexors provides a portion of the output mask. Selection controls for the multiplexors are generated from the most significant bits of the pointer to select the appropriate multiplexor input for each portion of the output mask. Unfortunately, even this solution may be cumbersome and slow, limiting its usefulness as operating frequencies of digital devices increase.
SUMMARY OF THE INVENTION
A mask generator circuit includes at least first and second mask generator circuits coupled to receive most significant and least significant sections of the pointer and to generate masks therefrom, and a plurality of circuits each configured to generate a region of the output mask from the mask generator circuit. The mask generated from the most significant bits section of the pointer (the most significant bits (MSB) mask) includes bits corresponding to various regions of the output mask. The plurality of circuits receive the MSB mask and the least significant bits (LSB) mask generated from the least significant bits section of the pointer and generate the output mask therefrom. The number of levels of logic required to generate the mask may be reduced, which may provide for mask generation at higher clock frequencies than previously possible. Furthermore, in certain embodiments, the number of gates used and the fanout on the signals may be limited, which may provide for scalability and low area usage.
Broadly speaking, a mask generator for generating an output mask having a transition between a binary one and a binary zero at a location in the output mask identified by a pointer provided to the mask generator is contemplated. The mask generator includes a first mask generator, a second mask generator, and a plurality of circuits coupled thereto. The first mask generator is coupled to receive a plurality of most significant bits of the pointer and is configured to generate a first mask in response thereto. Each bit of the first mask corresponds to a respective region of the output mask and is indicative, in a first state, that the transition either occurs in a less significant region than the respective region or occurs in the respective region. The bit is further indicative, in a second state, that the transition occurs in a more significant region of the output mask than the respective region. The second mask generator is coupled to receive a plurality of least significant bits of the pointer and is configured to generate a second mask in response thereto. The plurality of circuits are configured to generate the output mask responsive to the first and second masks. The plurality of circuits includes a first circuit configured to generate a first region of the output mask. The first circuit is coupled to receive a first bit of the first mask, the first bit corresponding to the first region of the output mask. The first circuit is further coupled to receive a second bit of the first mask, the second bit corresponding to a neighboring region to the first region, the neighboring region being a less significant region of the output mask. Additionally, the first circuit is coupled to receive bits of the second mask. The first circuit is configured to generate the first region of the output mask responsive to the first bit, the second bit, and the bits of the second mask.
Additionally, a method for generating an output mask having a transition between a binary one and a binary zero at a location in the output mask identified by a pointer is contemplated. A first mask is generated responsive to a plurality of most significant bits of the pointer. Each bit of the first mask corresponds to a respective region of the output mask and is indicative, in a first state, that the transition either occurs in a less significant region than the respective region or occurs in the respective region, and is further indicative, in a second state, that the transition occurs in a more significant region of the output mask than the respective region. A second mask is generated responsive to a plurality of least significant bits of the pointer. A first region of the output mask is generated responsive to: (i) a first bit of the first mask, the first bit corresponding to the first region of the output mask; (ii) a second bit of the first mask, the second bit corresponding to a neighboring region to the first region, the neighboring region being a less significant region of the output mask; and (iii) bits of the second mask.
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Advanced Micro Devices , Inc.
Malzahn David H.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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