Parallel layer 2 and layer 3 processing components in a...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C370S469000, C712S212000

Reexamination Certificate

active

10102960

ABSTRACT:
A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When both the L2 and L3 generation units complete their operations for a particular packet, a build component combines the generated L2 and L3 header information from the buffers to form a complete packet header.

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