Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-01-31
2001-12-11
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S159000
Reexamination Certificate
active
06329942
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an analog-to-digital converter (A/D) converter, and more particularly to an A/D converter that provides higher resolution levels.
BACKGROUND OF THE INVENTION
A/D converters, in general, operate according to a particular set of specifications. The most important of these are the resolution (number of bits) and the sampling frequency. For example, an 8-bit, 400 MHz A/D converter has a resolution of 8 bits and can produce 400 million digital outputs in one second. Flash architecture is one well known method of implementing a high-speed A/D converter. An example of flash architecture is disclosed in an article entitled “A 400 MHz input flash converter with error correction,”
IEEE Journal of Solid State Circuits
, Vol. 25, No. 1, pp. 184-191, Feb. 1990 (C. Mangelsdorf). A flash architecture requires 2
N
comparators for N bit resolution. Thus, a major drawback of the flash architecture is that the size of the converter essentially doubles if the resolution is increased by one bit. As a consequence, the power dissipation also roughly doubles, making it almost impractical to use this architecture for more than 10 bits of resolution.
Magnetic mass storage devices, such as disk drives, are used to store large amounts of data, especially in computer systems. Computer drives include a plurality of magnetized disks and a spindle motor to rotate the disks. Data is stored on concentric data tracks on the surfaces of the magnetized rotating disks. A sensor (usually referred to as a read/write head) positioned proximate to the rotating disk and movable in a radial direction is used to detect (i.e., read) information in the form of analog signals from the disks. An important aspect of the operation of the disk drive is the positioning or location of the read/write head with respect to the magnetized tracks on the rotating disk. A servo mechanism is used to determine and control the exact position of the read/write head with respect to the disk so that data can be read from or written onto a specific sector and track on a specific disk.
Generally, two types of data or information are stored on the disk drive. The first type is user data, and that data is read during a user mode. The second type is servo data which is the data used by the servo mechanism to determine the position of the read/write head with respect to a specific sector on a specific track of the disk. The servo data is read in a servo mode.
The electronics that are used for these two read modes vary widely from one manufacturer to another since there is no standard as to how the two processes should be implemented. Typically, when reading data in both the user mode and the servo mode, an analog signal detected by the read head is first input into a very low-noise preamplifier which amplifies the signal. The amplified signal is then input into a read channel circuit. The read channel circuit is typically a single integrated circuit (IC) which directs the amplified signal to either the read path, which processes the user data, or the servo path, which processes the servo data. In either case, the front end of the read channel includes a voltage gain amplifier (VGA) and a continuous-time filter (CTF), being common to both the servo and read signal processing.
The processing circuitry for the user data is generally self-contained within the read channel IC. However, only part of the servo processing is done within the read channel IC. The majority of the servo processing, such as DSP operations and voice coil motor driving, is performed by separate circuits using one or more ICs. Essential to the read channel processing or the servo processing is the A/D converter for digitizing the analog signals. The position of the A/D converter within the read channel has changed over the years, tending to be moved earlier and earlier within the path of signal processing. Consequently, there is a need for an A/D converter that can convert the analog signal to a digital signal in an extremely fast time.
FIG. 3
illustrates a circuit schematic of a conventional comparator used in conjunction with a high-speed flash A/D converter. It includes preamplifier
300
which amplifies the difference between the input signal and a reference voltage. The amplified difference signal output from the preamplifier
300
is applied to a latch circuit
302
that converts the small signal into a logic level signal. The preamplifier
300
is made up of one or two amplifier stages that amplify the input signal typically by a factor of 10 or 20.
FIG. 4
illustrates waveforms associated with the A/D converter of FIG.
3
. As can be seen from
FIG. 4
, when the clock signal is high, the latch
302
samples the output of the preamplifier
300
, and after the clock signal goes low, the strobe signal goes high, forcing the latch to the output of preamplifier
300
. This is followed by an Lreset signal during which the latch is reset. Thus, all the three operations, namely preamplification, latching and reset have to occur sequentially within one clock enterval. This leaves only a small interval for the latching operation. In high speed operations, this is insufficient to reach a complete decision whether the output is high or low. In very high-speed applications, the time available for latching, namely the time duration of the strb signal, may be insufficient to make a complete decision within this time.
SUMMARY OF THE INVENTION
An advantageous A/D converter that has a high level of resolution and high sampling speed is disclosed. The present invention includes a circuit to generate a plurality of reference signals, a circuit to compare the input signals with the reference signals and to produce digital signals corresponding to the difference between the input signals and the reference signals, and a multiplexer circuit for receiving the digital signals and outputting digital signals. Additionally, the present invention includes an encoder for encoding the output of the multiplexer circuit into N-bit digital signals. The present invention includes two latches in parallel. Each latch is connected to the same comparator.
REFERENCES:
patent: 4928103 (1990-05-01), Lane
patent: 5680133 (1997-10-01), Komatsu
patent: 5856800 (1999-01-01), LePailleur et al.
patent: 5877720 (1999-03-01), Setty et al.
patent: 6169504 (2001-01-01), Park
Martin David A.
Nagaraj Krishnasawamy
Brady W. James
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Williams Howard L.
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