Parallel keystream decoder

Details Parallel keystream decoder Parallel keystream decoder

2006-08-15

2006-08-15

Eddy, Elisca Pierre (Department: 3621)

Data processing: financial, business practice, management, or co

Business processing using cryptography

C705S051000, C705S057000

Reexamination Certificate

active

07092906

ABSTRACT:
Methods and circuitry are disclosed for decoding a keystream. A set of test bits is generated, and a set of attempted keystream bits are generated from differences between the test bits and an input set of cipher bits. A set of current keystream bits are generated from a current seed using a parallel feedback shift register, and the attempted keystream bits are compared to the current keystream bits. In response to attempted keystream bits being equal to the current keystream bits, the current keystream bits are fed back as a new current seed. In response to attempted keystream bits being not equal to the current keystream bits, the attempted keystream bits are fed back as the new current seed.

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patent: 5631960 (1997-05-01), Likens et al.
patent: 5757909 (1998-05-01), Park
patent: 6578150 (2003-06-01), Luyster
patent: 363039229 (1988-02-01), None
patent: 408023331 (1996-01-01), None

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