Parallel interconnect for planar arrays

Details Parallel interconnect for planar arrays Parallel interconnect for planar arrays

1978-11-29

1980-12-16

Abrams, Neil

Geometrical instruments

339 49B, H05K 108

Patent

active

042393124

ABSTRACT:
A large scale parallel architecture in which many parallel channels numbering 10.sup.2 or more operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stacked integrated circuit wafers having top and bottom surfaces, electric signal paths extending through each of the wafers between the surfaces, and micro-interconnects (smaller than 50 mil) on the surfaces of adjacent wafers interconnecting the respective electric signal paths with a topographical one-to-one correspondence.

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patent: 4045107 (1977-08-01), Sutherland
IBM Tech. Discl. Bulletin, Schneider, vol. 7, No. 4, p. 331, 9-1964.
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IBM Bulletin, Miller, vol. 8, No. 3, p. 380, 8-1965.
IBM Bulletin, Beverly, vol. 8, No. 10, p. 1325.

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