Parallel integrated frame synchronizer chip

Details Parallel integrated frame synchronizer chip Parallel integrated frame synchronizer chip

1997-09-02

2000-06-27

Ghebretinsae, Temesghen

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

370514, H04L 700

Patent

active

060815701

ABSTRACT:
A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.

REFERENCES:
patent: 4168469 (1979-09-01), Parikh et al.
patent: 4316285 (1982-02-01), Bobilin et al.
patent: 5646947 (1997-07-01), Cooper et al.
patent: 5668840 (1997-09-01), Takano
patent: 5715278 (1998-02-01), Croft et al.
Third International Symposium On Space Mission Operations and Ground Data Systems--Part 1, NASA Conference Publication 3281, Proceedings of a Conference Held at Greenbelt Marriott Hotel, Greenbelt, Maryland USA, Nov. 15-18, 1994.

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