Parallel integrated circuit test apparatus and test method

Details Parallel integrated circuit test apparatus and test method Parallel integrated circuit test apparatus and test method

2001-12-21

2004-05-04

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06731127

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to the testing of integrated circuits, and more particularly to an apparatus and method for testing sets of integrated circuits simultaneously with two or more testers.
BACKGROUND
Semiconductors are widely used to manufacture integrated circuits for electronic applications, including computers, radios, televisions, digital cameras, and personal computing devices, as examples. Such integrated circuits typically include multiple transistors fabricated in single crystal silicon. For example, there may be millions of semiconductor devices manufactured on a single semiconductor product. With the trend towards downsizing electronic devices, there is a need to manufacture smaller integrated circuits and package the integrated circuits in smaller packages. The manufacturing and testing of downsized integrated circuits and packages presents many challenges.
Integrated circuits are typically manufactured by depositing a plurality of conductive, insulative, and/or semiconductive material layers on a semiconductor substrate, and patterning the various material layers using lithography processes to form devices and interconnects that perform the electrical functions of the integrated circuit. Usually, hundreds or thousands of integrated circuits are manufactured on a single semiconductor wafer. The wafer is then tested, by a wafer probe test, for example, which tests single integrated circuits (IC's) on the wafer at a time, or groups of single IC's at a time.
The integrated circuits that pass the wafer probe test are packaged after singulation. Packaging is typically required because the integrated circuits are too small to be electrically coupled directly to printed circuit boards. Although usually, a single integrated circuit is packaged in a single package, alternatively, a plurality of integrated circuits may be packaged in a single package, known as a hybrid IC.
Typically, an integrated circuit is packaged by attaching the device to a substrate or some other material more rigid than the integrated circuit wafer material, often with the package being larger than the integrated circuit. The IC package usually comprises a plurality of contact terminals that may be used to couple the packaged integrated circuit to a printed circuit board or other device, depending on the application.
An example of a prior art IC test apparatus
100
is shown in FIG.
1
. Test apparatus
100
comprises a “high cost” test apparatus, referred to as “high cost” because of the high expense of the tester
108
, and therefore, the high expense per IC of running tests on IC's. The high cost test apparatus
100
may cost hundreds of thousands to millions of dollars (U.S. $), for example, and may be used to test packaged IC's.
The high cost test apparatus
100
includes an input station
102
coupled to a handler
104
, with an output station
106
coupled to the handler
104
on the opposite side. The test apparatus
100
includes a tester
108
which is typically a high cost piece of equipment that includes control circuitry and test electronics, and includes storage for storing the IC test information obtained. The test apparatus
100
includes a monitor
138
and console
142
adapted to receive instructions from and provide information and communicate test results to an operator. The monitor
138
and console
142
may be integral to the tester
108
or handler
104
, for example (not shown).
The test apparatus
100
includes a test head
110
that is coupled to the tester
108
by a cable or wiring
112
. The test head
110
is coupled to and interfaces with the handler
104
using load board
114
. The load board
114
is adapted to support packaged integrated circuits under test, and may comprise one or more sockets
116
adapted to support the integrated circuits or devices under test. The handler
104
may include an environmental chamber (not shown) for high and/or low temperature tests, and the handler
104
may also include robotic equipment such as pick and place machines and conveyor belts that are adapted to move IC's from the input station
102
through the handler
104
, to the load board sockets
116
, to the output station
106
.
The input station
102
may include a plurality of input IC trays
118
, with each input IC tray
118
being adapted to hold and support a plurality of IC's to be tested. An operator of the test apparatus
100
loads the input IC trays
118
with the IC's, for example, in an array of rows and columns. The input station
102
may include a pneumatic vacuum plunger
122
that is adapted to remove IC's from the input IC tray
118
and place them in the interim tray
124
, for example. The input station includes a robotic pick and place mechanism
120
that is adapted to facilitate the movement of the IC's from the input IC tray
118
using the plunger
122
.
IC's are transferred using the interim tray
124
into the handler
104
through the input port
126
. Inside the handler, the IC's are placed using robotic machinery in the sockets
116
on the load board
114
. After the IC's are tested, the robotic equipment moves the IC's back to the interim tray
124
or to another tray located near the output station
106
, and the IC's are moved to the output station through the output port
128
.
The tested IC's are placed using robotic pick and place mechanism
132
and plunger
134
into output IC trays
130
.
The test apparatus
100
shown is considered a high cost tester because not only is the apparatus
100
expensive, furthermore, a variety of rather complicated and time-consuming tests are performed on each device under test. The test procedures performed by high cost tester
100
may included detailed functional test of the IC's, and may include AC parameter tests, as examples. For digital signal processors (DSP's), which are complex IC devices, the IC's may have a large number of pins (e.g. 100 to over 500 pin), and require extensive testing. Some tests may require that the IC's be thermally soaked, e.g., brought up to a certain temperature, before certain tests are performed on the IC's. Thermal soaks are time-consuming, and therefore, particularly expensive tests.
Because the high cost test apparatus
108
is very expensive and the time spent testing an IC or set of IC's is very valuable, often, IC's are first screened using a low cost test apparatus before being tested on the high cost test apparatus
108
. Some tests may be off-loaded to the low cost tester, to save time on the high cost test apparatus
108
.
A prior art low cost test apparatus
200
is shown in FIG.
2
. The apparatus
200
is referred to as “low cost” because it is significantly less expensive than a high cost test apparatus
100
, e.g., {fraction (1/10)}th of the cost. For example, a low cost test apparatus
200
may cost a few tens of thousands of U.S. dollars.
Low cost test apparatus
200
includes a tester
236
that includes a monitor
238
, a control computer
240
which may comprise one or more Sparc station, for example, and a console
242
. The tester
236
is coupled by wiring
250
a test head
244
. The test head
244
is coupled to a handler
248
via a load board
246
. The load board
246
includes a of plurality sockets
252
that are adapted to support and make electrical contact to IC devices under test. An operator of the tester
236
loads the IC devices under test (DUT) into the load board
246
, couples the tester to the handler
248
, and instructs the tester, using the control computer
240
, to perform the low cost tests. Typically, in a low cost test apparatus
200
, a plurality of sockets
252
reside on the load board
246
, for example, there may be four or eight sockets
252
on a load board
246
, so that a set of IC's may be tested with the low cost tests.
The low cost test apparatus
200
may be used to weed out devices that fail preliminary or pre-screening tests. The low cost test apparatus
200
an

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