Patent
1996-07-12
1998-04-28
Lim, Krisna
395391, 395595, G06F 930
Patent
active
057457255
ABSTRACT:
A succession of instructions are distributed between a plurality of multistage execution paths in a computer system. Each instruction is given a tag to identify the position of the instruction in the sequence and the execution paths of both that instruction and the preceding instruction. On entering an instruction in one execution path, register values are transferred from registers in a path executing a preceding instruction prior to completion of execution of that preceding instruction.
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IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1, 1990, pp. 349-359, Sohi, G.S., "Instruction Issue Logic For High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers".
IEE Proceedings E. Computers & Digital Techniques, vol. 139, No. 5, Part E, Sep. 1, 1992, pp. 439-449, Steven G. B., et al., "IHARP: A Multiple Instruction Issue Processor".
Lim Krisna
Morris James H.
SGS-Thomson Microelectronics Limited
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