Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-02-03
2001-11-20
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C414S935000, C414S936000, C414S937000, C414S939000
Reexamination Certificate
active
06320402
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to inspection systems used during fabrication of integrated circuits, and more particularly, to networking a plurality of different inspection stations to a host server that controls the inspection stations to inspect semiconductor wafers in parallel for maximizing throughput during manufacture of integrated circuits.
BACKGROUND OF THE INVENTION
The present invention is described in relation to inspection stations used during photolithography processes for fabrication of integrated circuits on semiconductor wafers. However, the present invention may be used for other types of inspection stations used during other types of integrated circuit fabrication processes.
Photolithography is by now a commonly known process used during fabrication of integrated circuits on semiconductor wafers. Referring to
FIG. 1
, during a typical photolithography process, material is patterned on a plurality of semiconductor wafers, including a first semiconductor wafer
102
, a second semiconductor wafer
104
, and a third semiconductor wafer
106
, using a photoresist patterning process. The plurality of semiconductor wafers
102
,
104
, and
106
comprise a lot of semiconductor wafers that are processed as a batch of semiconductor wafers according to a respective recipe corresponding to that lot of semiconductor wafers. Although three semiconductor wafers
102
,
104
, and
106
are shown in
FIG. 1
for clarity of illustration, a lot of semiconductor wafers typically includes a higher number of semiconductor wafers.
Referring to
FIG. 1
, during a typical photolithography process, each of the semiconductor wafers
102
,
104
, and
106
is coated with photoresist (step
108
in FIG.
1
). Such photoresist is then exposed to an energy source, such as an ultraviolet light source for example, with a patterning mask on the photoresist to create a desired pattern of development on the photoresist (step
110
in FIG.
1
). The photoresist is then developed typically by immersing the semiconductor wafers
102
,
104
, and
106
in a developer solution (step
112
in FIG.
1
). Such steps for a typical photolithography process are known to one of ordinary skill in the art of integrated circuit fabrication.
Typically, the semiconductor wafers
102
,
104
, and
106
are inspected for proper photolithography processing in an ADI (After Development Inspection) process (step
114
in FIG.
1
). Such an inspection process typically includes a plurality of different types of inspections. If the lot of wafers
102
,
104
, and
106
passes the multiple inspections after the development step
112
, the photoresist on the wafers
102
,
104
, and
106
is then etched to pattern the developed photoresist on the wafers
102
,
104
, and
106
(step
116
in FIG.
1
). On the other hand, if the lot of wafers
102
,
104
, and
106
does not pass any of the multiple inspections after the development step
112
, the wafers
102
,
104
, and
106
are reworked to correct for such inspection failure (step
118
in FIG.
1
). The photolithography process may also include performing multiple inspections of the semiconductor wafers
102
,
104
, and
106
after the etch of the developed photoresist (step
120
in FIG.
1
). Such steps for a typical photolithography process are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 1 and 2
, in a typical prior art ADI (After Development Inspection) process, the lot of semiconductor wafers
102
,
104
, and
106
are inspected serially through a plurality of different inspection stations. (Elements having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function.) Each of the plurality of different inspection stations inspects a respective integrated circuit fabrication feature of a semiconductor wafer. For the ADI (After Development Inspection) process, the plurality of different inspection stations may include an overlay inspection station
202
, a critical dimension inspection station
204
, a micro feature inspection station
206
, a macro feature inspection station
208
, and a defect review inspection station
210
, as known to one of ordinary skill in the art of integrated circuit fabrication.
The overlay inspection station
202
checks whether a current mask pattern developed on the photoresist is properly aligned with a prior mask pattern etched in another layer of material on a semiconductor wafer. The critical dimension inspection station
204
checks whether the dimensions of the features developed on the photoresist is within a proper range. The micro feature inspection station
206
and the macro feature inspection station
208
check for the presence of defects on the semiconductor wafer after development of the photoresist. The micro feature inspection station
206
checks for defects that are less than approximately 50 &mgr;m (micrometers) in size, and the macro feature inspection station
208
checks for defects that are greater than approximately 50 &mgr;m (micrometers) in size.
The defect review inspection station
210
typically generates a count, classification, and/or mapping of defects on the semiconductor wafer. The defect review inspection station
210
may be provided by a vendor to be used after the inspection of the semiconductor wafer by the micro feature inspection station
206
and the macro feature inspection station
208
, as known to one of ordinary skill in the art of integrated circuit fabrication. Alternatively, the defect review inspection station
210
may be provided by a vendor to be used as part of the critical dimension inspection station
204
, as known to one of ordinary skill in the art of integrated circuit fabrication.
Such inspection stations are known to one of ordinary skill in the art of integrated circuit fabrication. In the prior art, such different inspection stations are typically stand-alone machines that may be available from different vendors. In the prior art, the semiconductor wafers
102
,
104
, and
106
are kept together as a lot as they are inspected through the inspection stations
202
,
204
,
206
,
208
, and
210
because of a desire by human operators to keep a lot of semiconductor wafers together during fabrication of the semiconductor wafers.
Thus, the lot of semiconductor wafers
102
,
104
, and
106
are all processed serially first through the overlay inspection station
202
, then through the critical dimension inspection station
204
, then through the micro feature inspection station
206
, then through the macro feature inspection station
208
, and then finally through the defect review inspection station
210
. In the prior art, a human operator typically carries the lot of semiconductor wafers
102
,
104
, and
106
to each of the inspection stations
202
,
204
,
206
,
208
, and
210
for inspection in such a serial order. At each inspection station, all of the semiconductor wafers of a lot may be inspected or a chosen one or a few of the semiconductor wafers of a lot may be inspected.
However, such a serial ADI (After Development Inspection) process of semiconductor wafers is slow. For example, such a current serial ADI (After Development Inspection) process takes approximately 4-5 hours for completing the ADI (After Development Inspection) process and is the bottle-neck in throughput of the photolithography process during manufacture of integrated circuits on semiconductor wafers. However, for maintaining quality control during manufacture of integrated circuits, each lot of semiconductor wafers goes through each of the multiple different inspection stations
202
,
204
,
206
,
208
, and
210
.
Thus, a mechanism is desired for further maximizing the throughput of semiconductor wafers through the multiple different inspection stations during manufacture of integrated circuits on semiconductor wafers.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a system for inspecting semiconductor wafers of at least one
MacCrae Nicholas R.
Matt Bernard
Phan Khoi A.
Brown Glenn W.
Hamdan Wasseem H.
LandOfFree
Parallel inspection of semiconductor wafers by a plurality... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel inspection of semiconductor wafers by a plurality..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel inspection of semiconductor wafers by a plurality... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2608674