Parallel-input/serial output CCD register with clocking noise ca

Details Parallel-input/serial output CCD register with clocking noise ca Parallel-input/serial output CCD register with clocking noise ca

1985-04-15

1986-04-22

Rubinson, Gene Z.

Facsimile and static presentation processing

Facsimile

Recording apparatus

358221, H04N 315

Patent

active

045846090

ABSTRACT:
Alternate ones of the charge transfer stages in the CCD output register of a solid-state imager are loaded with charge packets descriptive of the intensities of respective image elements. The intervening charge transfer stages are loaded with charge packets descriptive of a reference level. Subsequently, the CCD output register is operated as a shift register to serially supply charge packets to an electrometer. Successive samples of the electrometer response are differentially combined to obtain an output signal with undesired components suppressed therein.

REFERENCES:
patent: 4064533 (1977-12-01), Lampe et al.
patent: 4079423 (1978-03-01), Diehl
patent: 4498105 (1985-02-01), Crawshaw
patent: 4514766 (1985-04-01), Koike et al.
patent: 4527200 (1985-07-01), Takahashi et al.

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