Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Reexamination Certificate
2001-11-08
2004-05-25
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
C327S293000
Reexamination Certificate
active
06741193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates generally to a parallel in serial out (PISO) circuit for use in a digital data communication system, and more specifically to a PISO circuit which is suitable for use in a physical layer defined by IEEE (Institute of Electrical and Electronic Engineers) 1394 standard.
2. Description of Related Art
In order to comply with the demand for large volume transfer of digital data at a high speed between a personal computer and a peripheral(s) byway of example, the IEEE 1394-1995 Standard for a High Performance Serial Bus (hereinafter sometimes referred to as 1394 serial bus) was developed. As is known in the art, the 1394 serial bus protocols are described as a set of three stacked layers: transaction layer, link layer and physical layer. Explaining these layers in brief, the transaction layer defines a complete request-response control to perform the bus transactions. The link layer provides a one-way (half-duplex) data transfer with confirmation of request service to the transaction layer, and further provides addressing, data checking, and date framing for packet transmission and reception. On the other hand, the physical layer translates the logical symbols used by the link layer into electrical signals, and defines the mechanical interfaces for the serial bus. More specifically, the physical layer has three primary functions: transmission and reception of data bits, arbitration, and provision for the electrical and mechanical interface.
Before turning to the present invention, it is deemed preferable to briefly describe, with reference to FIGS.
1
-
6
(C), prior art to which the present invention is applicable.
Referring to
FIG. 1
, a conventional data transfer circuit (denoted by
10
) is schematically shown in block diagram form, which circuit is provided in the physical layer. As shown, the data transfer circuit
10
generally comprises a parallel in serial out (PISO) circuits
12
and
14
, a clock frequency divider
16
, a timing controller
18
, and a data'strobe encoder
20
, all of which are coupled as illustrated.
According to the IEEE 1394 protocol, the data transfer speed is selected among 400, 200 and 100 Mbps (Mega-bit per second). The cock frequency divider
16
, which takes the form of 3-stage counter using three flip-flops (FFs), receives a 400 MHz clock, and divides the same so as to output three different clocks that have respectively clock rates of 200 MHz, 100 MHz, and 50 MHz. In addition, the clock frequency divider
16
allows the inputted 400 MHz clock to pass therethrough. That is to say, the clock frequency divider
16
issues the four different clocks of 400 MHz, 200 MHz, 100 MHz and 50 MHz, all of which are applied to the timing controller
18
. These clocks are respectively denoted by CLK
400
, CLK
200
, CLK
100
, and CLK
50
in the instant disclosure.
The data/strobe encoder
20
is supplied with a parallel data DATA_Parallel of 8 bits (in the instant case) to be transmitted in serial, and outputs two parallel data: one is a parallel data DATA_Parallel which is exactly the same as the inputted parallel data; and the other is a parallel strobe signal STRB_Parallel. These parallel data DATA_Parallel and STRB_Parallel are applied to each of the PISO circuits
12
and
14
. Although not shown in
FIG. 1
, the parallel data (8 bits) are respectively numbered
0
,
1
,
2
, . . . ,
7
in order of sequential transmission from each of the PISO circuits
12
and
14
. The parallel strobe signal STRB_Parallel is produced by simply reversing a logic level of each of the odd number data bits (viz., data bits respectively numbered
1
,
3
,
5
, and
7
) of the parallel data of DATA_Parallel.
As mentioned above, according to the IEEE 1394 standard, two serial data DATA_Serial (Tx) and STRB_Serial (Tx), which are respectively outputted from the PISO circuits
12
and
14
, are transmitted at the transfer speed of 400, 200, or 100 Mbps using a lock rate of 400 MHz, 200 MHz, or 100 MHz. In order to select one of these clock rates, the timing controller
18
is supplied with data transfer speed control signals SPD
0
and SPD
1
, and also receives the above-mentioned four clocks CLK
400
, CLK
200
, CLK
100
, and CLD
50
. The speed control signals SPD
0
and SOD
1
will further be described later.
Referring to
FIG. 2
, the timing controller
18
of
FIG. 1
is shown in detail in block diagram form. As shown in
FIG. 2
, the timing controller
18
comprises decoders
22
a
-
22
c
, flip-flops (FFs)
24
a
-
24
e
, and selectors
26
a
-
26
c
, all of which are coupled as shown. As mentioned above, the controller
18
is supplied with the four locks CLK
400
, CLK
200
, CLK
100
, and CLK
50
, and further receives the data transfer speed control signals SPD
0
and SPD
1
from logic circuitry (not shown) provided in the physical layer. The timing controller
18
per se is not directly concerned with the present invention, and hence, only the brief description thereof will be given for the sake of simplifying the instant disclosure. The decoder
22
c
receives the data transfer speed control signals SPD
0
and SPD
1
, and issues data transfer speed control signals C
1
-C
3
. The control signal C
1
is applied to the selectors
26
a
and
26
c
, while the control signals C
2
and C
3
are both applied to each of the selectors
26
a
and
26
b.
The timing controller
18
can be divided into two sections in terms of function thereof. That is, the first section includes the flip-flop
24
e
and the selectors
26
b
-
26
c
, while the second section includes the decodes
22
a
-
22
b
, the flip-flops
24
a
-
24
d
, and the selector
26
a
. When both of the data transfer speed signals SPD
0
and SPD
1
is non-active, the output of the selector
26
c
of the first section becomes CLK
400
(400 MHz), and the output of the flip-flop
24
d
is 50 MHz (viz., one eight of 400 MHz). Further, when only SPD
1
becomes active, the output of the selector
26
c
is CLK
200
(200 MHz) and at the same time, the output of the flip-flop
24
d
is 25 MHz. Still further, when only SPD
0
becomes active, the output of the selector
26
c
becomes CLK
100
, and at the same time, the flip-flop
24
d
becomes 12.5 MHz. The clock and the data acquisition signal thus generated are both applied to the PISO circuits
12
and
14
.
FIG. 3
is a diagram showing the PISO circuit
12
in detail. It is to be noted that the other PISO circuit
14
is configured in exactly the same manner as the PISO circuit
12
. The PISO circuit
12
is a conventional type 8-bit shift register which is configured by eight flip-flops
30
a
-
30
h
, selectors
32
a
-
32
g
, and an AND gate
34
. A clock signal (400 MHz, 200 MHz, or 100 MHz) is applied t the clock terminals of the flip-fops
30
a
-
30
h
. Data bits D
0
-D
6
are respectively applied to the selectors
32
a
-
32
g
by way of input terminals T
0
-T
6
, and on the other hand, a data bit D
7
is applied to the AND gate
34
via an input terminal T
7
. When the data acquisition signal DAS is applied to the PISO circuit
12
, the flip-flops
30
a
-
30
h
acquire respectively the outputs of the preceding circuits. The contents of the flip-flops
30
a
-
30
h
are then shifted in synchronism with the clock until the data bit D
7
is outputted from the flip-flop
30
h
, and thereafter, these operations are repeated on the following eight parallel data (viz., D
8
-D
15
).
FIG. 4
is a timing chart graphically showing the above-mentioned operation of the PISO circuit
12
. It is clearly understood that the first 8-bit parallel data D
0
-D
7
are acquired at the flip-flops
30
a
-
30
h
at a time in response to the data acquisition signal DAS, after which the PISO circuit
12
outputs in series D
0
-D
7
in synchronism with the clock as DATA_Serial (Tx), and thereafter, the same operation is carried out on the following 8-bit parallel data D
8
-D
15
.
FIG. 5
is a timing chart showing the operation of the other PISO circuit
14
. As mentioned above, the parallel strobe data STRB_Parallel dif
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Wamsley Patrick
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