Parallel hierarchical timing correction

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364488, G06F 9455, H01L 2170, H01L 2702

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active

058779655

ABSTRACT:
A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.

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