Parallel graphics processor with workload distributing and depen

Details Parallel graphics processor with workload distributing and depen Parallel graphics processor with workload distributing and depen

1990-09-11

1991-04-23

Shaw, Dale M.

Boots, shoes, and leggings

3649261, 3649314, 3649354, 364518, G06F 1516

Patent

active

050105159

ABSTRACT:
An interactive 3-dimensional computer graphics display system has an arbitrary number of parallel connected graphic arithmetic processors (GAPS) coupled to an applications processor through a display list management module and coupled to an image memory unit that generates video output. High level commands from the applications processor are distributed for substantially equal temporal processing among the GAPS by delivering the commands to that GAP which is most ready to receive the next command. Each GAP has a FIFO input memory. A plurality of priority levels are established related to GAP FIFO input emptiness. An additional priority scheme is established within each FIFO emptiness level using a daisy-chained grant signal. A command bus includes dedicated lines for control signals between the GAPs to signal the priority and to pass along the grant signal. Sequentiality of the output from the GAPs is maintained by codes included in command headers and monitored by special tag FIFO memories resident on each GAP, which maintain an entry for each sequential command executed by any of the GAPs. The entry indicates that the command is sequential, and whether it is being executed by the GAP upon which the tag FIFO resides. A GAP output controller signals to all other GAPs when it has reached the stage where the next command it will send is a sequential command.

REFERENCES:
patent: 4172284 (1979-10-01), Heinrich et al.
patent: 4321666 (1982-03-01), Tasar et al.
patent: 4373183 (1983-02-01), Means et al.
patent: 4853877 (1989-08-01), Parkhurst et al.

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