Parallel encoding apparatus and method implementing cyclic redun

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371 375, G06F 1110

Patent

active

053832043

ABSTRACT:
In an error correction system, which incorporates Cyclic Redundancy Check (CRC) and a Reed-Solomon (RS) code, original data are encoded simultaneously by CRC and RS encoders. The CRC encoder processes the words 0-9 of the original data to form CRC check bytes, which become the last bytes in words 6, 7, 8 and 9. The RS encoder processes 104-byte words 0-9 of original data to form 16 redundant RS bytes per word. The words 0-5 are simultaneously supplied from a codeword memory to CRC and RS encoders. The redundant RS bytes generated by the RS encoder are sent back to the codeword memory, while the CRC encoder saves the CRC check bytes in local registers. For words 6-9 the RS encoder processes the bytes of original data and stops processing before the CRC bytes. It then temporarily saves the generated data in the codeword memory and waits for the CRC encoder to finish encoding. Once the CRC encoder completes, the CRC bytes corresponding to the words 6-9 are processed by the RS. encoder to finish each set of the redundant RS bytes.

REFERENCES:
patent: Re33462 (1990-11-01), Suzuki et al.
patent: 4633471 (1986-12-01), Perera et al.
patent: 4680764 (1987-07-01), Suzuki et al.
patent: 4951284 (1990-08-01), Abdel-Ghaffar et al.

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