Parallel distributed sample scrambling system

Cryptography – Key management – Having particular key generator

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380 43, 380 50, H04L 924

Patent

active

053554159

ABSTRACT:
A parallel distributed sample scrambling and descrambling system for fixed-sized packet transmission comprising a parallel scrambler and a parallel descrambler. The scrambler includes; a parallel shift register generator 61 for generating parallel sequences; a sampling means 62 for generating samples from said parallel shift register generator 61; a parallel scrambling means 63 for performing parallel scrambling function by modulo-2 adding the parallel sequences to parallel input data sequences; and a multiplexing means 64. The descrambler includes; a demultiplexing means 70; a parallel shift register generator 66 for generating parallel sequences; a sampling means 67 for generating samples from said parallel shift register generator 66; a comparing means 68 for comparing the samples transmitted from the scrambler with the samples generated by said sampling means 67; a correction means 65 for performing correction for samples at each correction time according to the comparison result from said comparing means; and a parallel descrambling means 69 for performing parallel descrambling of the scrambled data sequences by modulo-2 adding the parallel sequences to the scrambled data sequences.

REFERENCES:
patent: 4531022 (1985-07-01), Pioli
patent: 4755987 (1988-07-01), Lee et al.
Report: Parallel Scrambling Techniques for Digital Multiplexlers, AT&T Technical Journal, Author DooWhan Choi, 123-136.
"Self Synchronising Scrambler x.sup.43 +1" CCITT SG SVIII-Melbourne, 2-13, Dec. 1991.

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