Parallel distributed sample descrambling circuit for cell-based

Details Parallel distributed sample descrambling circuit for cell-based Parallel distributed sample descrambling circuit for cell-based

1994-03-16

1995-09-05

Barron, Jr., Gilberto

Cryptography

Key management

Having particular key generator

380 46, 380 49, 370107, H04L 926, H04J 306

Patent

active

054486408

ABSTRACT:
A parallel distributed sample descrambler part for a cell-based ATM physical layer, comprising a PRBS generator for generating an 8-bit random number when being set to any value other than "0" in response to an initial value set signal upon initialization, to execute a generation polynomial for distributed sample descrambling given by x.sup.31 +x.sup.28 +1, and a descrambler for adding 8 bits of reception data to 8 bits of the random number from the PRBS generator, respectively, to perform the descrambling of the reception data and outputting the descrambled data bits. A sample processor extracts two bits for synchronization of the descrambler from the 8-bit random number from the PRBS generator as first and second samples in response to an external sampling clock and an external synchronous clock. The sample processor also extracts highest first and second bits of a syndrome signal from a cell delineation part in a cell-based ATM physical layer receiver as transmitter PRBS samples in response to the external sampling clock and the external synchronous clock. The sample processor compares the extracted first and second samples and the extracted syndrome signal highest first and second bits with each other and outputs first and second synchronous signals for the PRBS generator in accordance with the compared result.

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patent: 5283831 (1994-02-01), Cook et al.
patent: 5321754 (1994-06-01), Fisher et al.
patent: 5349611 (1994-09-01), Varian
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