Parallel digital-to-analog-converter

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S137000, C708S410000, C342S400000

Reexamination Certificate

active

07372386

ABSTRACT:
A method for performing parallel digital-to-analog conversion of an n-bit digital input data signal at a frequency of fsincluding receiving the n-bit digital input data signal; generating M−1 delayed input data signals, M being the number of parallel conversions channels, the M−1 delayed input data signals having respective increasing amount of unit delay, the digital input data signal and the M−1 delayed input data signals forming M digital signals; holding the M digital signals for a first time period; performing a data transformation of the M digital signals using an M×M Hadamard matrix; generating M (n+m)-bit transformed digital data signals; converting each of the M transformed digital data signals to M analog signals; and performing a reverse data transformation of the M analog signals based on the M×M Hadamard matrix to generate an output analog signal indicative of the n-bit digital input data signal.

REFERENCES:
patent: 3795864 (1974-03-01), Fulton Jr.
patent: 6411645 (2002-06-01), Lee et al.
patent: 6525682 (2003-02-01), Yap et al.
patent: 6765533 (2004-07-01), Szajnowski
patent: 2006/0279445 (2006-12-01), Kinyua et al.
William C. Black Jr. et al., “Time Interleaved Converter Arrays,” IEEE International Solid-State Circuits Conference, Feb. 1980, pp. 14-15 and 254.
William C. Black Jr. et al., “Time Interleaved Converter Arrays,” IEEE Journal of Solid-State Circuits, vol. SC-15, No. 6, Dec. 1980, pp. 122-1029.
Naoki Kurosawa et al.,“Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems,” Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 48, No. 3, Mar. 2001, pp. 261-271.
Daihong Fu et al., “A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 1904-1911.
Kenneth C. Dyer et al., “An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 1912-1919.
G. Manganaro, “Feed-forward approach for timing skew in interleaved and double-sampled circuits,” Electronics Letters, vol. 37, No. 9, Apr. 26, 2001, pp. 552-554.
Gabriele Bernardinis et al., “Dynamic Stage Matching for Parallel Pipeline A/D Converters,” 2002 IEEE, Symp. On Circuits and Systems, vol. I, pp. 905-908, month unknown.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Parallel digital-to-analog-converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel digital-to-analog-converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel digital-to-analog-converter will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2814986

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.