Parallel digital processor including lateral transfer buses with

Details Parallel digital processor including lateral transfer buses with Parallel digital processor including lateral transfer buses with

1990-02-09

1993-09-21

Kriess, Kevin A.

Boots, shoes, and leggings

395325, 364DIG1, 3642287, 3642319, 3642283, 3642281, 364229, 3642294, 364240, 3642402, 3642407, G06F 1516

Patent

active

052476898

ABSTRACT:
A digital computer system including a large number of parallel processing modules (PPM's). Each PPM includes an arithmetic logic unit (ALU), an instruction decoder, and internal bus switching. The main memory is organized in columns and rows with a separate column for each PPM port. Each PPM preferably includes at least three ports to permit parallel transfer of instructions and data to the PPM's. The ports of the PPM's are also connected to segmented lateral transfer buses which operate in conjunction with the internal bus switching of the PPM's to permit tandem ALU operation.

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