Parallel digital processing for reducing delay in SAR ADC logic

Details Parallel digital processing for reducing delay in SAR ADC logic Parallel digital processing for reducing delay in SAR ADC logic

2007-05-31

2008-10-21

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

07439898

ABSTRACT:
The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

REFERENCES:
patent: 5675340 (1997-10-01), Hester et al.
patent: 6809674 (2004-10-01), Ramsden
patent: 6950047 (2005-09-01), Piasecki et al.
patent: 6958722 (2005-10-01), Janakiraman et al.
patent: 7023372 (2006-04-01), Singh et al.

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