Parallel decimator adaptive filter and method for all-rate...

Details Parallel decimator adaptive filter and method for all-rate... Parallel decimator adaptive filter and method for all-rate...

2005-05-03

2005-05-03

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S322000, C708S319000

Reexamination Certificate

active

06889238

ABSTRACT:
Parallel adaptive filters and filtering methods that enable processing of an input signal in a circuit that has an clock speed many times slower than the input rate of the input signal that is processed. A polyphase decimator structure processes a data stream requiring a low pass filtered bandlimited (low-rate) output that is used for high-rate output structures. The filters and methods break an input data stream into parallel paths that efficiently produce a bandlimited (decimated, low-rate) filtered output. Each of the parallel paths is processed at a decimated rate to provide a filtered output signals corresponding to a filtered version of the input signal.

REFERENCES:
patent: 5235647 (1993-08-01), Van de Kerkhof
patent: 6356569 (2002-03-01), Sonalkar et al.
patent: 6426983 (2002-07-01), Rakib et al.
patent: 20030118134 (2003-06-01), Harris

Affiliated with

Also associated with

Rating

Parallel decimator adaptive filter and method for all-rate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel decimator adaptive filter and method for all-rate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel decimator adaptive filter and method for all-rate... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3413748