Parallel decimation circuits

Details Parallel decimation circuits Parallel decimation circuits

2006-10-17

2006-10-17

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S290000

Reexamination Certificate

active

07124159

ABSTRACT:
A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

REFERENCES:
patent: 6347233 (2002-02-01), Solar et al.
patent: 6470365 (2002-10-01), Rahman et al.
patent: 6859813 (2005-02-01), Gorbics et al.
“Acquisition Clock Dithering in a Digital Oscilloscope”. Dereck E. Toeppen, Hewlett-Packard Journal, vol. 48, No. 2, Apr. 2, 1997, pp. 1-4.

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