Parallel decimation circuits

Details Parallel decimation circuits Parallel decimation circuits

2005-02-22

2005-02-22

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S290000

Reexamination Certificate

active

06859813

ABSTRACT:
A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

REFERENCES:
patent: 6347233 (2002-02-01), Solar et al.
patent: 6470365 (2002-10-01), Rahman et al.

Affiliated with

Also associated with

Rating

Parallel decimation circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel decimation circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel decimation circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3498148